DS90CR218 Datasheet, PDF (9/12 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link Receiver - 75 MHz

Applications Information
The DS90CR217 and DS90CR218 are backward compatible
with the existing 5V Channel Link transmitter/receiver pair
(DS90CR213, DS90CR214). To upgrade from a 5V to a 3.3V
system the following must be addressed:
1. Change 5V power supply to 3.3V. Provide this supply to
the V_CC, LVDS V_CC and PLL V_CC.
2. Transmitter input and control inputs except 3.3V TTL/
CMOS levels. They are not 5V tolerant.
3. The receiver powerdown feature when enabled will lock
receiver output to a logic low. However, the 5V/66 MHz
receiver maintain the outputs in the previous state when
powerdown occurred.
The Channel Link devices are intended to be used in a wide
variety of data transmission applications. Depending upon
the application the interconnecting media may vary. For
example, for lower data rate (clock rate) and shorter cable
lengths (< 2m), the media electrical performance is less
critical. For higher speed/long distance applications the me-
dia’s performance becomes more critical. Certain cable con-
structions provide tighter skew (matched electrical length
between the conductors and pairs). Twin-coax for example,
has been demonstrated at distances as great as 5 meters
and with the maximum data transfer of 1.58 Gbit/s. Addi-
tional applications information can be found in the following
National Interface Application Notes:
AN = ####
AN-1041
AN-1108
AN-806
AN-905
AN-916
Topic
Introduction to Channel Link
PCB Design Guidelines for LVDS and
Link Devices
Transmission Line Theory
Transmission Line Calculations and
Differential Impedance
Cable Information
CABLES: A cable interface between the transmitter and
receiver needs to support the differential LVDS pairs. The
21-bit CHANNEL LINK chipset (DS90CR217/218) requires
four pairs of signal wires and the 28-bit CHANNEL LINK
chipset (DS90CR287/288) requires five pairs of signal wires.
The ideal cable/connector interface would have a constant
100Ω differential impedance throughout the path. It is also
recommended that cable skew remain below 130ps (@ 75
MHz clock rate) to maintain a sufficient data sampling win-
dow at the receiver.
In addition to the four or five cable pairs that carry data and
clock, it is recommended to provide at least one additional
conductor (or pair) which connects ground between the
transmitter and receiver. This low impedance ground pro-
vides a common-mode return path for the two devices.
Some of the more commonly used cable types for point-to-
point applications include flat ribbon, flex, twisted pair and
Twin-Coax. All are available in a variety of configurations and
options. Flat ribbon cable, flex and twisted pair generally
perform well in short point-to-point applications while Twin-
Coax is good for short and long applications. When using
ribbon cable, it is recommended to place a ground line
between each differential pair to act as a barrier to noise
coupling between adjacent pairs. For Twin-Coax cable ap-
plications, it is recommended to utilize a shield on each
cable pair. All extended point-to-point applications should
also employ an overall shield surrounding all cable pairs
regardless of the cable type. This overall shield results in
improved transmission parameters such as faster attainable
speeds, longer distances between transmitter and receiver
and reduced problems associated with EMS or EMI.
The high-speed transport of LVDS signals has been demon-
strated on several types of cables with excellent results.
However, the best overall performance has been seen when
using Twin-Coax cable. Twin-Coax has very low cable skew
and EMI due to its construction and double shielding. All of
the design considerations discussed here and listed in the
supplemental application notes provide the subsystem com-
munications designer with many useful guidelines. It is rec-
ommended that the designer assess the tradeoffs of each
application thoroughly to arrive at a reliable and economical
cable solution.
BOARD LAYOUT: To obtain the maximum benefit from the
noise and EMI reductions of LVDS, attention should be paid
to the layout of differential lines. Lines of a differential pair
should always be adjacent to eliminate noise interference
from other signals and take full advantage of the noise
canceling of the differential signals. The board designer
should also try to maintain equal length on signal traces for
a given differential pair. As with any high-speed design, the
impedance discontinuities should be limited (reduce the
numbers of vias and no 90 degree angles on traces). Any
discontinuities which do occur on one signal line should be
mirrored in the other line of the differential pair. Care should
be taken to ensure that the differential trace impedance
match the differential impedance of the selected physical
media (this impedance should also match the value of the
termination resistor that is connected across the differential
pair at the receiver’s input). Finally, the location of the
CHANNEL LINK TxOUT/RxIN pins should be as close as
possible to the board edge so as to eliminate excessive pcb
runs. All of these considerations will limit reflections and
crosstalk which adversely effect high frequency performance
and EMI.
TERMINATION: Use of current mode drivers requires a
terminating resistor across the receiver inputs. The CHAN-
NEL LINK chipset will normally require a single 100Ω resistor
between the true and complement lines on each differential
pair of the receiver input. The actual value of the termination
resistor should be selected to match the differential mode
characteristic impedance (90Ω to 120Ω typical) of the cable.
Figure 10 shows an example. No additional pull-up or pull-
down resistors are necessary as with some other differential
technologies such as PECL. Surface mount resistors are
recommended to avoid the additional inductance that ac-
companies leaded resistors. These resistors should be
placed as close as possible to the receiver input pins to
reduce stubs and effectively terminate the differential lines.
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