DS90CR218 Datasheet, PDF (8/12 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link Receiver - 75 MHz

AC Timing Diagrams (Continued)
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 6) + ISI (Inter-symbol interference) (Note 7)
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Note 6: Cycle-to-cycle jitter is less than 250 ps at 75MHz
Note 7: ISI is dependent on interconnect length; may be zero
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FIGURE 9. Receiver LVDS Input Skew Margin (DS90CR217/DS90CR218)
DS90CR218 Pin Description—Channel Link Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DWN
V_CC
GND
PLL V_CC
PLL GND
LVDS V_CC
LVDS GND
I/O No.
Description
I
3 Positive LVDS differential data inputs. (Note 8)
I
3 Negative LVDS differential data inputs. (Note 8)
O 21 TTL level data outputs.
I
1 Positive LVDS differential clock input.
I
1 Negative LVDS differential clock input.
O
1 TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT.
I
1 TTL level input. When asserted (low input) the receiver outputs are low.
I
4 Power supply pins for TTL outputs.
I
5 Ground pins for TTL outputs.
I
1 Power supply for PLL.
1
2 Ground pin for PLL.
I
1 Power supply pin for LVDS inputs.
I
3 Ground pins for LVDS inputs.
Note 8: These receivers have input failsafe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under these conditions
receiver inputs will be in a HIGH state. If a clock signal is present, outputs will all be HIGH; if the clock input is also floating/terminated outputs will remain in the last
valid state. A floating/terminated clock input will result in a LOW clock output.
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