DS90CR216A_04 Datasheet, PDF (9/13 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link-66 MHz, +3.3V Rising Edge Strobe LVDS Receiver 21-Bit Channel Link-66 MHz

AC Timing Diagrams (Continued)
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 6) + ISI (Inter-symbol interference) (Note 7)
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Note 6: Cycle-to-cycle jitter is less than TBD ps at 66 MHz.
Note 7: ISI is dependent on interconnect length; may be zero.
FIGURE 11. Receiver LVDS Input Skew Margin
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