DS90CP04 Datasheet, PDF (9/18 Pages) National Semiconductor (TI) – 4x4 Low Power 2.5 Gb/s LVDS Digital Cross-Point

ؾితಛੑ ( ͖ͭͮ)
ಛهͷͳ͍ݶΓɺਪ঑ಈ࡞৚݅ͷిిݯѹͱಈ࡞पғԹ౓Λର৅
Symbol
Parameter
Conditions
Min
SWITCHING CHARACTERISTICS á´· LVDS OUTPUTS (Figures 3, 5, 6)
t_SEL
SELx to OUT ʶ
Configuration select to new data at
OUT ʶ .
SWITCHING CHARACTERISTICS á´· Serial control Interface (Figures 4, 8, 9)
F_SCLK
T_DCCLK
SCLK Clock Frequency
CSCLK Duty Cycle
RSCLK Duty Cycle
0
Input SCLK Duty Cycle set at 50ˋ
45
t_S
SI–SCLK or MODE–SCLK Setup From SI or MODE Input Data to
Time
SCLK Rising Edge
1.5
t_H
SCLK–SI or SCLK–MODE Hold From SCLK Rising Edge to SI or
Time
MODE Input Data
1
t_DSO
SCLK to RSO or CSO Delay
From SCLK to RSO or CSO
1.5
t_DSCLK
SCLK to RSCLK or CSCLK
Delay
From SCLK to RSCLK or CSCLK
4.0
t_DSDIF
T_RISE
|SCLK to RSCLK or CSCLK– Propagation Delay Difference
SCLK to RSO or CSO|
between t_DSO and t_DSCLK
1.5
Logic Low to High Transition
Time
20ˋ to 80ˋ at RSO, CSO, RSCLK,
or CSCLK
T_FALL
Logic High to Low Transition
Time
80ˋ to 20ˋ at RSO, CSO, RSCLK,
or CSCLK
Typ
(Note 2)
50
1.5
1.5
Max
150
100
55
4
8.5
4.5
Units
ns
MHz
ˋ
ns
ns
ns
ns
ns
ns
ns
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
ʮઈର࠷େఆ֨ʯͱ͸ɺ͜ͷ஋Λ௒͑ΔͱσόΠεͷ҆શΛอোͰ͖ͳ੍͍ݶ஋Λҙຯ͠·͢ɻσόΠε͕͜ͷ֨ن஋Ͱਖ਼ৗʹಈ࡞͢Δ͜ͱΛҙຯͯ͠
͍ΔΘ͚Ͱ͸͋Γ·ͤΜɻ
୅ද஋͸ V_DD ʹ 2.5VɺT_A ʹ 25 ˆͰଌఆ͞Ε͍ͯ·͢ɻ ୅ද஋͸ࢀরΛ໨తͱ͓ͯ͠Γɺ੡଄࣌ࠪݕ͸ߦ͍ͬͯ·ͤΜɻ
ࠩಈग़ྗిѹ V_OD ͸ |OUT ʴʵ OUT ʵ |ͱͯ͠ఆٛ͞Ε͍ͯ·͢ɻ ࠩಈೖྗ V_ID ͸ |IN ʴʵ IN ʵ |ͱͯ͠ఆٛ͞Ε͍ͯ·͢ɻ
ग़ྗΦϑηοτిѹ V_OS ͸ɺLVDS γϯάϧɾΤϯυग़ྗͷ࿦ཧ HIGH ిѹͱ࿦ཧ LOW ిѹͷฏͯ͠ͱۉఆٛ͞Ε͍ͯ·͢ɻ
೚ҙͷೖྗ͔Β೚ҙͷ 1 ͭͷࠩಈ LVDS ग़ྗʹର͢ΔɺنఆͷσʔλϨʔτͱσʔλύλʔϯͰಈ࡞͍ͯ͠Δͱ͖ͷ࢓༷نఆͰɺ͜ͷͱ͖࢒Γͷ 3 νϟω
ϧ͸ࢼݧର৅νϟωϧͱ͸ඇಉظͷ 1.25Gb/s ͷ K28.5 ύλʔϯͰಈ࡞͍ͤͯ͞·͢ɻδολ͸ɺ੡଄࣌ʹࠪݕ͸ͳ͞Ε·ͤΜ͕ɺαϯϓϧʹ΋ͱͮ͘ಛ
ੑΛ௨ͯ͠อূ͞Ε͍ͯ·͢ɻϥϯμϜɾδολ͸ 1,000 ճ෼ͷώετάϥϜͷϐʔΫɾπʔɾϐʔΫͱͯ͠ଌఆ͞Ε·͢ɻͳ͓ K28.5 ύλʔϯ͸ɺϏοτɾε
τϦʔϜ 0011111010 1100000101 ͷ܁Γฦ͠Ͱ͢ɻ ֬ఆతδολ (DJ ύλʔϯ ) ͸ɺαϯϓϧճ਺ 350 ճͷώετάϥϜͷฏͯ͠ͱۉଌఆ͞Ε͍ͯ·͢ɻ
૯δολ (TJ) ͸ɺ3,500 ճ෼ͷώετάϥϜͰɺϥϯμϜɾδολͱಉ༷ʹϐʔΫɾπʔɾϐʔΫͱͯ͠ଌఆ͞Ε͍ͯ·͢ɻ
FIGURE 2. Differential Driver DC Test Circuit
9
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