DS90CF563 Datasheet, PDF (9/12 Pages) National Semiconductor (TI) – LVDS 18-Bit Color Flat Panel Display (FPD) Link─ 65 MHz

AC Timing Diagrams (Continued)
FIGURE 13. Transmitter LVDS Output Pulse Position Measurement
DS012615-16
DS012615-17
SW — Setup and Hold Time (Internal Data Sampling Window)
TCCS — Transmitter Output Skew
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)
Cable Skew — typically 10 ps–40 ps per foot
FIGURE 14. Receiver LVDS Input Skew Margin
FIGURE 15. Seven Bits of LVDS in One Clock Cycle
DS012615-18
9
www.national.com