DS90CF563 Datasheet, PDF (5/12 Pages) National Semiconductor (TI) – LVDS 18-Bit Color Flat Panel Display (FPD) Link─ 65 MHz

Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
CLHT
CHLT
RCOP
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RSKM
RPDD
Parameter
CMOS/TTL Low-to-High Transition Time (Figure 4)
CMOS/TTL High-to-Low Transition Time (Figure 4)
RxCLK OUT Period
RxCLK OUT High Time
RxCLK OUT Low Time
RxOUT Setup to RxCLK OUT
RxOUT Hold to RxCLK OUT
RxCLK IN to RxCLK OUT Delay @ 25˚C, V_CC = 5.0V
(Figure 10)
Receiver Phase Lock Loop Set (Figure 12)
RxIN Skew Margin (Note 6) (Figure 14)
Receiver Powerdown (Figure 17)
f = 65 MHz
f = 65 MHz
f = 65 MHz
f = 65 MHz
V_CC = 5V, T_A =25˚C
Min Typ Max Units
2.5
4.0
ns
2.0
3.5
ns
15
T
50
ns
7.8
9
ns
3.8
5
ns
2.5 4.2
ns
4.0 5.2
ns
6.4
10.7
ns
10
ms
600
ps
1
µs
Note 6: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output skew (TCCS)
and the setup and hold time (internal data sampling window), allowing for LVDS cable skew dependent on type/length and source clock (TxCLK IN) jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle)
AC Timing Diagrams
FIGURE 1. “Worst Case” Test Pattern
DS012615-4
5
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