DS90CF363B_06 Datasheet, PDF (9/11 Pages) National Semiconductor (TI) – +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link - 65MHz

DS90CF363B Pin Descriptions — FPD Link Transmitter
Pin Name
TxIN
TxOUT+
TxOUT−
FPSHIFT IN
TxCLK OUT+
TxCLK OUT−
PWR DOWN
V_CC
GND
PLL V_CC
PLL GND
LVDS V_CC
LVDS GND
NC
I/O No.
Description
I
21 TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
O
3 Positive LVDS differential data output.
O
3 Negative LVDS differential data output.
I
1 TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
O
1 Positive LVDS differential clock output.
O
1 Negative LVDS differential clock output.
I
1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down. See Applications Information section.
I
4 Power supply pins for TTL inputs.
I
4 Ground pins for TTL inputs.
I
1 Power supply pin for PLL.
I
2 Ground pins for PLL.
I
1 Power supply pin for LVDS outputs.
I
3 Ground pins for LVDS outputs.
1 No connect
Applications Information
The DS90CF363B are backward compatible with the
DS90C363/DS90CF363A and are a pin-for-pin replacement.
This device may also be used as a replacement for the
DS90CF563 (5V, 65MHz) and DS90CF561 (5V, 40MHz)
FPD-Link Transmitters with certain considerations/
modifications:
1. Change 5V power supply to 3.3V. Provide this supply to
the V_CC, LVDS V_CC and PLL V_CC of the transmitter.
TRANSMITTER INPUT PINS
The DS90CF363B transmitter input and control inputs ac-
cept 3.3V LVTTL/LVCMOS levels. They are not 5V tolerant.
TRANSMITTER INPUT CLOCK/DATA SEQUENCING
The DS90CF363B does not require any special requirement
for sequencing of the input clock/data and PD (PowerDown)
signal. The DS90CF363B offers a more robust input se-
quencing feature where the input clock/data can be inserted
after the release of the PD signal. In the case where the
clock/data is stopped and reapplied, such as changing video
mode within Graphics Controller, it is not necessary to cycle
the PD signal. However, there are in certain cases where the
PD may need to be asserted during these mode changes. In
cases where the source (Graphics Source) may be supply-
ing an unstable clock or spurious noisy clock output to the
LVDS transmitter, the LVDS Transmitter may attempt to lock
onto this unstable clock signal but is unable to do so due the
instability or quality of the clock source. The PD signal in
these cases should then be asserted once a stable clock is
applied to the LVDS transmitter.Asserting the PWR DOWN
pin will effectively place the device in reset and disable the
PLL, enabling the LVDS Transmitter into a power saving
standby mode. However, it is still generally a good practice
to assert the PWR DOWN pin or reset the LVDS transmitter
whenever the clock/data is stopped and reapplied but it is
not mandatory for the DS90CF363B.
SPREAD SPECTRUM CLOCK SUPPORT
The DS90CF363B can support Spread Spectrum Clocking
signal type inputs. The DS90CF363B outputs will accurately
track Spread Spectrum Clock/Data inputs with modulation
frequencies of up to 100KHz (max.)with either center spread
of ±2.5% or down spread -5% deviations.
POWER SOURCES SEQUENCE
In typical applications, it is recommended to have V_CC, LVDS
V_CC and PLL V_CC from the same power source with three
separate de-coupling bypass capacitor groups. There is no
requirement on which VCC entering the device first.
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