DS90CF363B_06 Datasheet, PDF (3/11 Pages) National Semiconductor (TI) – +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link - 65MHz

Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min Typ Max Units
TRANSMITTER SUPPLY CURRENT
ICCTG Transmitter Supply Current
16 Grayscale
ICCTZ Transmitter Supply Current
Power Down
R_L = 100Ω,
C_L = 5 pF,
16 Grayscale Pattern
f = 25 MHz
(Figures 2, 4 ) " Typ " f = 40 MHz
values are given for V
CC = 3.6V and T _A =
+25˚C, " Max " values
f = 65 MHz
are given for V _CC =
3.6V and T _A = −10˚C
Power Down = Low
Driver Outputs in TRI-STATE^® under
Power Down Mode
28
40
mA
32
45
mA
39
50
mA
11
150
µA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V_CC = 3.3V and T _A = +25˚C unless specified otherwise.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V_OD and ∆V_OD ).
Note 4: V_OS previously referred as V_CM.
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
TCIT
TxCLK IN Transition Time (Figure 5 )
TCIP
TxCLK IN Period (Figure 6 )
TCIH
TxCLK IN High Time (Figure 6 )
TCIL
TxCLK IN Low Time (Figure 6 )
TXIT
TxIN, and Power Down pin transition Time
TXPD
Minimum pulse width for Power Down pin signal
Min
14.7
0.35T
0.35T
1.5
1
Typ
T
0.5T
0.5T
Max
5
50.0
0.65T
0.65T
6.0
Units
ns
ns
ns
ns
ns
us
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
LLHT
LVDS Low-to-High Transition Time (Figure 4 )
LHLT
LVDS High-to-Low Transition Time (Figure 4 )
TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5)
TPPos1 Transmitter Output Pulse Position for Bit 1
f = 65 −0.20
MHz _2.00
TPPos2 Transmitter Output Pulse Position for Bit 2
4.20
TPPos3 Transmitter Output Pulse Position for Bit 3
6.39
TPPos4 Transmitter Output Pulse Position for Bit 4
8.59
TPPos5 Transmitter Output Pulse Position for Bit 5
10.70
TPPos6 Transmitter Output Pulse Position for Bit 6
12.99
TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5)
TPPos1 Transmitter Output Pulse Position for Bit 1
f = 40 −0.25
MHz _3.32
TPPos2 Transmitter Output Pulse Position for Bit 2
6.89
TPPos3 Transmitter Output Pulse Position for Bit 3
10.46
TPPos4 Transmitter Output Pulse Position for Bit 4
14.04
TPPos5 Transmitter Output Pulse Position for Bit 5
17.61
TPPos6 Transmitter Output Pulse Position for Bit 6
21.18
Typ
0.75
0.75
0
2.20
4.40
6.59
8.79
10.99
13.19
0
3.57
7.14
10.71
14.29
17.86
21.43
Max
1.4
1.4
+0.20
2.40
4.60
6.79
8.99
11.19
13.39
+0.25
3.82
7.39
10.96
14.54
18.11
21.68
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
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