DP83934CVUL-20 Datasheet, PDF (89/104 Pages) National Semiconductor (TI) – MHz SONICTM-T Systems-Oriented Network Interface Controller with Twisted Pair Interface

9 0 AC and DC Specifications (Continued)
BUS RETRY
TL F 11719 – 70
Number
Parameter
20 MHz
Min
Max
25 MHz
Min
Max
Units
T41
Bus Retry Synchronous Setup Time to BSCK
(Note 3)
5
4
ns
T41a
Bus Retry Asynchronous Setup Time
6
5
ns
to BSCK (Note 3)
T42
Bus Retry Hold Time from BSCK (Note 2)
7
6
ns
Note 1 Depending upon the mode the SONIC-T will assert and deassert HOLD from the rising or falling edge of BSCK
Note 2 Unless Latched Bus Retry mode is set (LBR in the Data Configuration Register Section 4 3 2) BRT must remain asserted until after the Th state If
Latched Bus Retry mode is used BRT does not need to satisfy T42
Note 3 T41 is for synchronous bus retry and T41a is for asynchronous bus retry (see Section 4 3 2 bit 15 Extended Bus Mode) Since T41a is an asynchronous
setup time it is not necessary to meet it but doing so will guarantee that the bus exception occurs in the current memory transfer not the next
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