DP83934CVUL-20 Datasheet, PDF (29/104 Pages) National Semiconductor (TI) – MHz SONICTM-T Systems-Oriented Network Interface Controller with Twisted Pair Interface

5 0 Buffer Management (Continued)
All RRA registers are concatenated with the URRA register
for generating the full 32-bit address
The resource descriptors that the system writes to the RRA
consists of four fields (1) RXrsrc buff ptr0 (2)
RXrsrc buff ptr1 (3) RXrsrc buff wc0 and (4)
RXrsrc buff wc1 The fields must be contiguous (they can-
not straddle the end points) and are written in the order
shown in Figure 5-9 The ‘‘0’’ and ‘‘1’’ in the descriptors
denote the least and most significant portions for the Buffer
Pointer and Word Count The first two fields supply the
32-bit starting location of the Receive Buffer Area (RBA)
and the second two define the number of 16-bit words that
the RBA occupies
Note that two restrictions apply to the Buffer Pointer and
Word Count First in 32-bit mode since the SONIC-T al-
ways writes long words an even count must be written to
RXrsrc buff wc0 Second the Buffer Pointer must either
be pointing to a word boundary in 16-bit mode (A0e0) or a
long word boundary in 32-bit mode (A0 A1e0 0) Note also
that the descriptors must be properly aligned in the RRA as
discussed in Section 5 3
the SONIC-T to begin receive processing at the first de-
scriptor An example of two descriptors linked together is
shown in Figure 5-10 The fields initialized by the system are
displayed in bold type The other fields are written by the
SONIC-T after a packet is accepted The RXpkt in use
field is first written by the system and then by the SONIC-T
Note that the descriptors must be aligned properly as dis-
cussed in Section 5 3 Also note that the URDA register is
concatenated with the CRDA register to generate the full
32-bit address
TL F 11719 – 20
FIGURE 5-9 RRA Initialization
After configuring the RRA the RRA Read command (setting
RRRA bit in the Command register) may be given This
command causes the SONIC-T to read the RRA descriptor
in a single block operation and load the following registers
(see Section 6 2 for register mnemonics)
w CRBA0 register RXrsrc buff ptr0
w CRBA1 register RXrsrc buff ptr1
w RBWC0 register RXrsrc buff wc0
w RBWC1 register RXrsrc buff wc1
When the command has completed the RRRA bit in the
Command register is reset to ‘‘0’’ Generally this command
is only issued during initialization At all other times the RRA
is automatically read as the SONIC-T finishes using an RBA
5 4 4 3 Initializing The RDA
To accept multiple packets from the network the receive
packet descriptors must be linked together via the
RXpkt link fields Each link field must be written with a 15-bit
(A15 – A1) pointer to locate the beginning of the next de-
scriptor in the list The LSB of the RXpkt link field is the End
Of List (EOL) bit and is used to indicate the end of the
descriptor list EOL e 1 for the last descriptor and EOL e 0
for the first or middle descriptors The RXpkt in use field
indicates whether the descriptor is owned by the SONIC-T
The system writes a non-zero value to this field when the
descriptor is available and the SONIC-T writes all ‘‘0’s’’
when it finishes using the descriptor At startup the Current
Receive Descriptor Address (CRDA) register must be load-
ed with the address of the first RXpkt status field in order for
TL F 11719 – 21
FIGURE 5-10 RDA Initialization Example
5 4 4 4 Initializing the Lower Boundary of the RBA
A ‘‘false bottom’’ is set in the RBA by loading the End Of
Buffer Count (EOBC) register with a value equal to the maxi-
mum size packet in words (16 bits) that may be received
This creates a lower boundary in the RBA Whenever the
Remaining Buffer Word Count (RBWC0 1) registers decre-
ment below the EOBC register the SONIC-T buffers the
next packet into another RBA This also guarantees that a
packet is always contiguously buffered into a single Receive
Buffer Area (RBA) The SONIC-T does not buffer a packet
into multiple RBAs Note that in 32-bit mode the SONIC-T
holds the LSB always low so that it properly compares with
the RBWC0 1 registers
After a hardware reset the EOBC reset the EOBC register
is automatically initialized to 2F8h (760 words or 1520
bytes) For 32-bit applications this is the suggested value for
EOBC EOBC defaults to 760 words (1520 bytes) instead of
759 words (1518 bytes) because 1518 is not a double word
(32-bit) boundary (see Section 5 4 2 1) If the SONIC-T is
used in 16-bit mode then EOBC should be set to 759 words
(1518 bytes) because 1518 is a word (16-bit) boundary
Sometimes it may be desired to buffer a single packet per
RBA When doing this it is important to set EOBC and the
buffer size correctly The suggested practice is to set EOBC
to a value that is at least 4 bytes in 32-bit mode or 2 bytes
in 16-bit mode less than the buffer size An example of this
for 32-bit mode is to set EOBC to 760 words (1520 bytes)
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