DP83865_04 Datasheet, PDF (82/86 Pages) National Semiconductor (TI) – 10/100/1000 Ethernet Physical Layer

7.0 Frequently Asked Questions
7.1 Do I need to access any MDIO register to start
up the PHY?
A: The answer is no. The PHY is a self contained device.
The initial settings of the PHY are configured by the strap-
ping option at the pins. The PHY will start normal operation
based on the strapping options upon power up or reset.
7.2 I am trying to access the registers through
MDIO and I got invalid data. What should I do?
A: There are a number of items that you need to check.
— Make sure the MDC frequency is not greater than 2.5
MHz.
— Check if the MDIO data line has a 2K pull up resistor and
the line is idling high.
— Verify the data timing against the datasheet.
— Be sure the turn around time (TA) is at least 1 bit long.
7.3 Why can the PHY establish a valid link but can
not transmit or receive data?
A: PHY is a self contained device. The PHY can establish
link by itself without any MAC and management involve-
ment. Here are some suggestions to isolate the problem.
— Use MDIO management access to configure the BIST
registers to transmit packet. If link partner can receive
data, the problem may lie in the MAC interface.
— Check the MAC transmit timing against the PHY
datasheet.
— Verify the receive timing of the MAC device to see if it
matches the PHY datasheet.
— If the PHY receives the data correctly, the activity LED
should turn on.
— Start the debugging at the slower 10 Mbps or 100 Mbps
speed.
— Enable the loopback at register 0x00.14. Verify that you
can receive the data that you transmit.
7.4 What is the difference between TX_CLK,
TX_TCLK, and GTX_CLK?
A: All the 3 clocks above are related to transmitting data.
However, their functions are different:
TX_CLK: The TX_CLK is an output of the PHY and is part
of the MII interface as described in IEEE 802.3u specifica-
tion, Clause 28.
This is used for 10/100 Mbps transmit activity. It has two
separate functions:
— It is used to synchronize the data sent by the MAC and
to latch this data into the PHY.
— It is used to clock transmit data on the twisted pair.
GTX_CLK: The GTX_CLK is an output of the MAC and is
part of the GMII interface as described in IEEE 802.3z
specification, Clause 35.
This is used for 1000 Mbps transmit activity. It has only one
function:
— It is used to synchronize the data sent by the MAC and
to latch this data into the PHY.
The GTX_CLK is NOT used to transmit data on the twisted
pair wire. For 1000 Mbps operation, the Master PHY uses
the internal 125 MHz clock generated from the CLOCK_IN
clock to transmit data on the wire. The Slave PHY uses the
clock recovered from the link partner’s transmission as the
transmit clock for all four pairs.
TX_TCLK: The TX_TCLK is an output of the PHY and can
be enabled to come out on pin 6 (during Test Mode 2 and 3
it is automatically enabled). This is a requirement from the
IEEE 802.3ab specification, Clause 40.6.1.2.5.
This is used for 1000 Mbps transmit activity. It has only one
function:
— It is used in “Test Modes 2 & 3” to measure jitter in the
data transmitted on the wire.
Either the reference clock or the clock recovered from
received data is used for transmitting data; depending on
whether the PHY is in MASTER or SLAVE mode.
TX_TCLK represents the actual clock being used to trans-
mit data.
7.5 What happens to the TX_CLK during 1000
Mbps operation? Similarly what happens to
RXD[4:7] during 10/100 Mbps operation?
A: TX_CLK is not used during the 1000 Mbps operation,
and the RXD[4:7] lines are not used for the 10/100 opera-
tion. These signals are outputs of the Gig PHYTER V. To
simplify the MII/GMII interface, these signals are driven
actively to a zero volt level. This eliminates the need for
pull-down resistors.
7.6 What happens to the TX_CLK and RX_CLK
during Auto-Negotiation and during idles?
A: During Auto-Negotiation the Gig PHYTER V drives a 25
MHz clock on the TX_CLK and RX_CLK lines. After a valid
link is established and during idle time, these lines are
driven at 2.5 MHz in 10 Mbps, and at 25 MHz in 100 Mbps
mode. In 1000 Mbps mode only RX_CLK is driven at 125
MHz.
7.7 Why doesn’t the Gig PHYTER V complete
Auto-Negotiation if the link partner is a forced
1000 Mbps PHY?
A: IEEE specifications define “parallel detection” for 10/100
Mbps operation only. Parallel detection is the name given
to the Auto-Negotiation process where one of the link part-
ners is Auto-Negotiating while the other is in forced 10 or
100 Mbps mode. In this case, it is expected that the Auto-
Negotiating PHY establishes half-duplex link at the forced
speed of the link partner.
However, for 1000 Mbps operation this parallel detection
mechanism is not defined. Instead, any 1000BASE-T PHY
can establish 1000 Mbps operation with a link partner in the
following two cases:
— When both PHYs are Auto-Negotiating,
— When both PHYs are forced 1000 Mbps. Note that one
of the PHYs is manually configured as MASTER and the
other is manually configured as SLAVE.
7.8 What determines Master/Slave mode when
Auto-Negotiation is disabled in 1000Base-T
mode?
A: Disabling 1000 Base-T Auto-Negotiation forces the PHY
to operate in Master or Slave mode. The selection is
through MULTI_EN pin. Since there is no way of knowing
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