DP83865_04 Datasheet, PDF (21/86 Pages) National Semiconductor (TI) – 10/100/1000 Ethernet Physical Layer

2.0 Register Block (Continued)
2.3 Register Description
In the register description under the ‘Default’ heading, the following definitions hold true:
— RW
— RO
— LH
— LL
— SC
—P
— STRAP[x]
= Read Write access
= Read Only access
= Latched High until read, based upon the occurrence of the corresponding event
= Latched Low until read, based upon the occurrence of the corresponding event
= Register sets on event occurrence (or is manually set) and Self-Clears when event ends
= Register bit is Permanently set to a default value
= Default value read from Strapped value at device pin at Reset, where x may take the values:
[0] internal pull-down
[1] internal pull-up
Table 3. Basic Mode Control Register (BMCR) address 0x00
Bit
Bit Name
Default
Description
15
Reset
0, RW, SC Reset:
1 = Initiate software Reset / Reset in Process.
0 = Normal operation.
This bit sets the status and control registers of the PHY to their
default states. This bit, which is self-clearing, returns a value of
one until the reset process is complete (approximately 1.2 ms for
reset duration). Reset is finished once the Auto-Negotiation pro-
cess has begun or the device has entered it’s forced mode.
14
Loopback
0, RW
Loopback:
1 = Loopback enabled.
0 = Normal operation.
The loopback function enables MII/GMII transmit data to be rout-
ed to the MII/GMII receive data path. The data loops around at
the DAC/ADC Subsystem (see block diagram page 2), bypassing
the Drivers/Receivers block. This exercises most of the PHY’s in-
ternal logic.
13
Speed[0]
STRAP[0], RW Speed Select:
When Auto-Negotiation is disabled, bits 6 and 13 select device
speed selection per table below:
Speed[1]
Speed[0]
Speed Enabled
1
1
= Reserved
1
0
= 1000 Mbps
0
1
= 100 Mbps
0
0
= 10 Mbps
(The default value of this bit is = to the strap value of pin 7 during
reset/power-on IF Auto-Negotiation is disabled.)
12
AN_EN
STRAP[1], RW Auto-Negotiation Enable:
1 = Auto-Negotiation Enabled - bits 6, 8 and 13 of this register are
ignored when this bit is set.
0 = Auto-Negotiation Disabled - bits 6, 8 and 13 determine the link
speed and mode.
(The default value of this bit is = to the strap value of pin 10 during
reset/power-on.)
21
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