DS90CR288 Datasheet, PDF (8/12 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link Receiver - 75 MHz

AC Timing Diagrams (Continued)
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)(Note 6) + ISI (Inter-symbol interference)(Note 7)
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Note 6: Cycle-to-cycle jitter is less than 250ps at 75MHz.
Note 7: ISI is dependent on interconnect length; may be zero
FIGURE 9. Receiver LVDS Input Skew Margin (DS90CR287/DS90CR288A)
DS90CR288 Pin Description—Channel Link Receiver
DS100872-20
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DWN
V_CC
GND
PLL V_CC
PLL GND
LVDS V_CC
LVDS GND
I/O No.
I
4
I
4
O 28
I
1
I
1
O
1
I
1
I
4
I
5
I
1
I
2
I
1
I
3
Description
Positive LVDS differential data inputs. (Note 8)
Negative LVDS differential data inputs. (Note 8)
TTL level data outputs.
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
Note 8: These receivers have input failsafe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under these conditions
receiver inputs will be in a HIGH state. If a clock signal is present, outputs will all be HIGH; if the clock input is also floating/terminated outputs will remain in the last
valid state. A floating/terminated clock input will result in a LOW clock output.
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