LP3931 Datasheet, PDF (7/17 Pages) National Semiconductor (TI) – Dual RGB LED Driver with High Current Boost DC-DC Converter

Logic Interface Characteristics
(1.8V ≤ V_{DD_IO} ≤ V_DD1,2)
Symbol
Parameter
Conditions
LOGIC INPUTS SS, SI, SCK, PWM_LED
V_IL
Input Low Level
V_IH
Input High Level
I_I
Logic Input Current
f_SCK
Clock Frequency
LOGIC INPUT NRST
V_{DD_IO} = 2.775V
V_IL
Input Low Level
V_IH
Input High Level
I_I
Logic Input Current
t_NRST
Reset Pulse Width
LOGIC OUTPUT SO
V_OL
Output Low Level
I_SO = 3 mA
V_OH
Output High Level
I_SO = − 3 mA
SPI Interface
LP3931 is compatible with the SPI serial bus specification
and it operates as a slave. The transmission consists of
16-bit Write and Read Cycles. One cycle consists of 7 Ad-
dress bits, 1 Read/Write (R/W) bit and 8 Data bits. R/W bit
high state defines a Write Cycle and low defines a Read
Cycle. SO output is normally in high-impedance state and it
is active only when Data is sent out during a Read Cycle. A
pull-up or pull-down resistor may be needed in SO line if a
Min
Typ
Max
Units
V_{DD_IO} − 0.5
−1.0
0.5
V
V
1.0
µA
13
MHz
1.5
−1.0
10
0.5
V
V
1.0
µA
µs
0.3
0.5
V
V_{DD_IO} − 0.5
V_{DD_IO} − 0.3
V
floating logic signal can cause unintended current consump-
tion in the input where SO is connected. The Address and
Data are transmitted MSB first. The Slave Select signal SS
must be low during the Cycle transmission. SS resets the
interface when high and it has to be taken high between
successive Cycles. Data is clocked in on the rising edge of
the SCK clock signal, while data is clocked out on the falling
edge of SCK.
SPI Write Cycle
20117307
SPI Read Cycle
7
20117308
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