LMK01000 Datasheet, PDF (7/18 Pages) National Semiconductor (TI) – 1.6 GHz High Performance Clock Buffer, Divider, and Distributor

Symbol
V_IH
V_IL
I_IH
I_IL
t_CS
t_CH
t_CWH
t_CWL
t_ES
t_CES
t_EWH
Parameter
Conditions
Digital MICROWIRE Interfaces (Note 11)
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
V_IH = Vcc
V_IL = 0
MICROWIRE Timing
Data to Clock Set Up Time
See Data Input Timing
Data to Clock Hold Time
See Data Input Timing
Clock Pulse Width High
See Data Input Timing
Clock Pulse Width Low
See Data Input Timing
Clock to Enable Set Up Time
See Data Input Timing
Enable to Clock Set Up Time
See Data Input Timing
Enable Pulse Width High
See Data Input Timing
Min Typ Max Units
1.6
Vcc
V
0.4
V
-5.0
5.0
µA
-5.0
5.0
µA
25
ns
8
ns
25
ns
25
ns
25
ns
25
ns
25
ns
Note 4: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 5: See section 3.2 for more current consumption / power dissipation calculation information.
Note 6: For all frequencies the slew rate, SLEW_CLKin1, is measured between 20% and 80%.
Note 7: The noise floor of the divider is measured as the far out phase noise of the divider. Typically this offset is 40 MHz, but for lower frequencies this
measurement offset can be as low as 5 MHz due to measurement equipment limitations. If the delay is used, then use section 1.3.
Note 8: Specification is guaranteed by characterization and is not tested in production.
Note 9: See characterization plots to see how this parameter varies over frequency.
Note 10: Applies to GOE, LD, and SYNC*.
Note 11: Applies to CLKuWire, DATAuWire, and LEuWire.
Serial Data Timing Diagram
30042803
Data bits set on the DATAuWire signal are clocked into a shift register, MSB first, on each rising edge of the CLKuWire signal. On
the rising edge of the LEuWire signal, the data is sent from the shift register to the addressed register determined by the LSB bits.
After the programming is complete the CLKuWire, DATAuWire, and LEuWire signals should be returned to a low state. The slew
rate of CLKuWire, DatauWire, and LEuWire should be at least 30 V/µs.
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