LMD18200_05 Datasheet, PDF (7/14 Pages) National Semiconductor (TI) – 3A, 55V H-Bridge

Application Information (Continued)
SIGNAL TRANSITION REQUIREMENTS
To ensure proper internal logic performance, it is good prac-
tice to avoid aligning the falling and rising edges of input
signals. A delay of at least 1 µsec should be incorporated
between transitions of the Direction, Brake, and/or PWM
input signals. A conservative approach is be sure there is at
least 500ns delay between the end of the first transition and
the beginning of the second transition. See Figure 4.
01056804
FIGURE 2. Locked Anti-Phase PWM Control
Sign/magnitude PWM consists of separate direction (sign)
and amplitude (magnitude) signals (see Figure 3). The (ab-
solute) magnitude signal is duty-cycle modulated, and the
absence of a pulse signal (a continuous logic low level)
represents zero drive. Current delivered to the load is pro-
portional to pulse width. For the LMD18200, the DIRECTION
input (pin 3) is driven by the sign signal and the PWM input
(pin 5) is driven by the magnitude signal.
01056805
FIGURE 3. Sign/Magnitude PWM Control
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