DS90C387A_06 Datasheet, PDF (7/19 Pages) National Semiconductor (TI) – Dual Pixel LVDS Display Interface/FPD-Link

AC Timing Diagrams
FIGURE 1. “Worst Case” Test Pattern
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FIGURE 2. “16 Grayscale” Test Pattern (Notes 7, 8, 9)
Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 8: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 9: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
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