COP8CBR9 Datasheet, PDF(67/84 Page) National Semiconductor (TI) – 8-Bit CMOS Flash Microcontroller with 32k Memory, Virtual EEPROM, 10-Bit A/D and Brownout

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COP8CBR9 Datasheet, PDF (67/84 Pages) National Semiconductor (TI) – 8-Bit CMOS Flash Microcontroller with 32k Memory, Virtual EEPROM, 10-Bit A/D and Brownout

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19.0 Memory Map (Continued)

Address

S/ADD REG

xxB8

xxB9

xxBA

xxBB

xxBC

xxBD

xxBE

xxBF

xxC0

xxC1

xxC2

xxC3

xxC4

xxC5

xxC6

xxC7

xxC8

xxC9

xxCA

xxCB

xxCC

xxCD

xxCE

xxCF

xxD0

xxD1

xxD2

xxD3

xxD4

xxD5

xxD6

xxD7

xxD8

xxD9

xxDA

xxDB

xxDC

xxDD to xxDF

Contents

USART Transmit Buffer (TBUF)

USART Receive Buffer (RBUF)

USART Control and Status Register

(ENU)

USART Receive Control and Status

USART Interrupt and Clock Source

USART Baud Register (BAUD)

USART Prescale Select Register (PSR)

Reserved for USART

Timer T2 Lower Byte

Timer T2 Upper Byte

Timer T2 Autoload Register T2RA Lower

Byte

Timer T2 Autoload Register T2RA Upper

Byte

Timer T2 Autoload Register T2RB Lower

Byte

Timer T2 Autoload Register T2RB Upper

Byte

Timer T2 Control Register

WATCHDOG Service Register

(Reg:WDSVR)

MIWU Edge Select Register

(Reg:WKEDG)

MIWU Enable Register (Reg:WKEN)

MIWU Pending Register (Reg:WKPND)

A/D Converter Control Register (ENAD)

A/D Converter Result Register High Byte

(ADRSTH)

A/D Converter Result Register Low Byte

(ADRSTL)

Reserved

Idle Timer Control Register (ITMR)

Port L Data Register

Port L Configuration Register

Port L Input Pins (Read Only)

Reserved for Port L

Port G Data Register

Port G Configuration Register

Port G Input Pins (Read Only)

Reserved

Port C Data Register

Port C Configuration Register

Port C Input Pins (Read Only)

Reserved for Port C

Port D

Reserved for Port D

Address

S/ADD REG

Contents

xxE0

Reserved

xxE1

Flash Memory Write Timing Register

(PGMTIM)

xxE2

ISP Key Register (ISPKEY)

xxE3 to xxE5 Reserved

xxE6

Timer T1 Autoload Register T1RB Lower

Byte

xxE7

Timer T1 Autoload Register T1RB Upper

Byte

xxE8

ICNTRL Register

xxE9

MICROWIRE/PLUS Shift Register

xxEA

Timer T1 Lower Byte

xxEB

Timer T1 Upper Byte

xxEC

Timer T1 Autoload Register T1RA Lower

Byte

xxED

Timer T1 Autoload Register T1RA Upper

Byte

xxEE

CNTRL Control Register

xxEF

PSW Register

xxF0 to FB On-Chip RAM Mapped as Registers

xxFC

X Register

xxFD

SP Register

xxFE

B Register

xxFF

S Register

0100 to 017F On-Chip 128 RAM Bytes

0200 to 027F On-Chip 128 RAM Bytes

0300 to 037F On-Chip 128 RAM Bytes

0400 to 0047F On-Chip 128 RAM Bytes

0500 to 057F On-Chip 128 RAM Bytes

0600 to 067F On-Chip 128 RAM Bytes

0700 to 077F On-Chip 128 RAM Bytes

Note: Reading memory locations 0070Hâ007FH (Segment 0) will return all

ones. Reading unused memory locations 0080Hâ0093H (Segment 0)

will return undefined data. Reading memory locations from other Seg-

ments (i.e., Segment 8, Segment 9, â¦ etc.) will return undefined data.

20.0 Instruction Set

20.1 INTRODUCTION

This section defines the instruction set of the COP8 Family

members. It contains information about the instruction set

features, addressing modes and types.

20.2 INSTRUCTION FEATURES

The strength of the instruction set is based on the following

features:

â¢ Mostly single-byte opcode instructions minimize program

size.

â¢ One instruction cycle for the majority of single-byte in-

structions to minimize program execution time.

â¢ Many single-byte, multiple function instructions such as

DRSZ.

â¢ Three memory mapped pointers: two for register indirect

addressing, and one for the software stack.

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