COP8CBR9 Datasheet, PDF (14/84 Pages) National Semiconductor (TI) – 8-Bit CMOS Flash Microcontroller with 32k Memory, Virtual EEPROM, 10-Bit A/D and Brownout

8.0 Electrical Characteristics (Continued)
AC Electrical Characteristics (−40˚C ≤ T_A ≤ +85˚C) (Continued)
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Parameter
Conditions
Min
Typ
Timer 1 Input Low Time
1
Timer 2, 3 Input High Time (Note 6)
1
Timer 2, 3 Input Low Time (Note 6)
1
Output Pulse Width
Timer 2, 3 Output High Time
150
Timer 2, 3 Output Low Time
150
USART Bit Time when using External
CKX
6 CKI
periods
USART CKX Frequency when being
Driven by Internal Baud Rate Generator
Reset Pulse Width
1
t_C = instruction cycle time.
Max
Units
t_C
MCLK or t_C
MCLK or t_C
ns
ns
2
MHz
t_C
Note 2: Maximum rate of voltage change must be < 0.5 V/ms.
Note 3: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to V_CC
and outputs driven low but not connected to a load.
Note 4: The HALT mode will stop CKI from oscillating. Measurement of I_DD HALT is done with device neither sourcing nor sinking current; with L. A. B, C, E, F, G0,
and G2–G5 programmed as low outputs and not driving a load; all D outputs programmed low and not driving a load; all inputs tied to V_CC; A/D converter and clock
monitor and BOR disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.
Note 5: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > V_CC and the pins will have sink current to V_CC when
biased at voltages > V_CC (the pins do not have source current when biased at a voltage below V_CC). These two pins will not latch up. The voltage at the pins must
be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients.
Note 6: If timer is in high speed mode, the minimum time is 1 MCLK. If timer is not in high speed mode, the minimum time is 1 t_C.
Note 7: Absolute Maximum Ratings should not be exceeded.
Note 8: V_cc must be valid and stable before G6 is raised to a high voltage.
A/D Converter Electrical Characteristics (−40˚C ≤ T_A ≤ +85˚C unless
otherwise noted) (Single-ended mode only)
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Parameter
Conditions
Min
Typ
Max
Units
Resolution
DNL
DNL
INL
INL
Offset Error
Offset Error
Gain Error
Gain Error
Input Voltage Range
Analog Input Leakage Current
Analog Input Resistance (Note 9)
V_CC = 5V
V_CC = 3V,
−20˚C ≤ T_A ≤ +85˚C
V_CC = 5V
V_CC = 3V,
−20˚C ≤ T_A ≤ +85˚C
V_CC = 5V
V_CC = 3V,
−20˚C ≤ T_A ≤ +85˚C
V_CC = 5V
V_CC = 3V,
−20˚C ≤ T_A ≤ +85˚C
2.7V ≤ V_CC < 5.5V
0
10
Bits
±1
LSB
±1
LSB
±3
LSB
±4
LSB
+2.5, −1
LSB
±2.5
LSB
+0.5, −2.5
LSB
±2.5
LSB
V_CC
V
0.5
µA
6k
Ω
Analog Input Capacitance
Conversion Clock Period
4.5V ≤ V_CC < 5.5V
0.8
2.7V ≤ V_CC < 4.5V
1.2
7
pF
30
µs
30
µs
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