LP3470 Datasheet, PDF (6/8 Pages) National Semiconductor (TI) – Tiny Power On Reset Circuit

Application Information
RESET TIMEOUT PERIOD
The Reset Timeout Period (t_RP) is programmable using an
external capacitor (C₁) connected to pin SRT of LP3470. A
Ceramic chip capacitor rated at or above 10V is sufficient.
The Reset Timeout Period (t_RP) can be calculated using the
following formula:
t_RP (ms) = 2000 x C₁ (µF).
For example a C₁ of 100 nF will achieve a t_RP of 200 ms. If
no delay due to t_RP is needed in a certain application, the pin
SRT should be left floating.
RESET OUTPUT
In applications like microprocessor (µP) systems, errors
might occur in system operation during power-up, power-
down, or brownout conditions. It is imperative to monitor the
power supply voltage in order to prevent these errors from
occurring.
The LP3470 asserts a reset signal whenever the V_CC supply
voltage is below a threshold (V_RTH) voltage. Reset is guar-
anteed to be a logic low for V_CC > 0.5V. Once V_CC exceeds
the reset threshold, the reset is kept asserted for a time
period (t_RP) programmed by an external capacitor (C₁); after
this interval Reset goes to logic high. If a brownout condition
occurs (monitored voltage falls below the reset threshold
minus a small hysteresis), Reset goes low. When V_CC re-
Timing Diagram
turns above the reset threshold, Reset remains low for a time
period t_RP before going to logic high.
PULL-UP RESISTOR SELECTION
The LP3470’s Reset output structure is a simple open-drain
N-channel MOSFET switch. A pull-up resistor (R₁) should be
connected to V_CC.
R₁ should be large enough to limit the current through the
output MOSFET (Q₁) below 10 mA. A resistor value of more
than 680Ω guarantees this. R₁ should also be small enough
to ensure a logic high while supplying all the leakage current
through the Reset pin. A resistor value of less than 68kΩ
satisfies this condition. A typical pull-up resistor value of 20
kΩ is sufficient in most applications.
NEGATIVE-GOING V_CC TRANSIENTS
The LP3470 is relatively immune to short duration negative-
going V_CC transients (glitches). The Typical Operating Char-
acteristics show the Maximum Transient Duration vs. Nega-
tive Transient Amplitude (graph titled Transient Rejection),
for which reset pulses are not generated. This graph shows
the maximum pulse width a negative-going V_CC transient
may typically have without causing a reset pulse to be
issued. As the transient amplitude increases (i.e. goes far-
ther below the reset threshold), the maximum allowable
pulse width decreases. A 0.1 µF bypass capacitor mounted
close to V_CC provides additional transient immunity.
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