LM4308 Datasheet, PDF (6/26 Pages) Texas Instruments – LM4308 Mobile Pixel Link Two (MPL-2) 18-bit CPU Display Interface Master/Slave

Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2)
Symbol
Parameter
Conditions
Min
Typ
PARALLEL BUS TIMING See alsoTable 2 and Figure 9
t_SET
t_HOLD
t_RISE
Set Up Time
Hold Time
Rise Time
Master Input, WRITE
RD* and WR* Slave V_DDIO = 1.6V
Outputs(Note 4) RDS = H
C_L = 15 pF,
Figure 2
V_DDIO = 3.0V
RDS = L
5
5
7
7
t_FALL
Fall Time
V_DDIO = 1.6V
7
RDS = H
V_DDIO = 3.0V
6
RDS = L
SERIAL BUS TIMING
t_DVBC
Data Valid before DC Clock
t_DVAC
Data Valid after DC Clock
t_Sset
Serial Set Time
t_Shold
Serial Hold Time
t_T
Transition Time
POWER UP TIMING
Master
(Note 9)
Slave
(Note 8)
Master
20% to 80%
26%
26%
400
400
200
t_a
DC ON High Delay
Link Start Up Sequence
128
t_b
DC Low Delay
128
t_c
DC Active Delay
504
t_d
DD High Delay
128
t_e
DD Low Delay
8
t_f
DD Differential ON
128
t_SU
Start Up Delay
Includes PLL Lock Time
POWER OFF TIMING
t_O
Turn Off Delay
t_a +t_b + t_c + t_d + t_e + t_f
(Note 7)
1,024
0.1
Max
74%
74%
2
Units
ns
ns
ns
ns
ns
ns
UI
UI
ps
ps
ps
CLK
cycles
CLK
cycles
CLK
cycles
CLK
cycles
CLK
cycles
CLK
cycles
CLK
cycles
µs
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