LM4308 Datasheet, PDF (1/26 Pages) Texas Instruments – LM4308 Mobile Pixel Link Two (MPL-2) 18-bit CPU Display Interface Master/Slave

September 2007
LM4308
Mobile Pixel Link Two (MPL-2) – 18-bit CPU Display
Interface Master/Slave
General Description
The LM4308 device adapts a 18-bit CPU style display inter-
faces to a MPL-2 SLVS differential serial link for displays. Two
chip selects support a main and sub display up to and beyond
640 x 480 pixels. A mode pin configures the device as a Mas-
ter (MST) or Slave (SLV). Both WRITE and READ operations
are supported. CPU interface widths below 18-bits are sup-
ported by tieing unused inputs to a static level.
The differential line drivers and receivers conform to the
JEDEC SLVS Standard. When noise is picked up as com-
mon-mode, it is rejected by the receivers. This is further
enhanced with the 50 Ohm output impedance of the drivers.
The 100 Ohm termination is integrated into the receivers.
Data integrity is insured with a 5-bit CRC field. CRC checking
is done for both WRITE and READ operations. An Error
(ERR) pin reports the occurrence of an error. A Write Only
mode is also provided.
The interconnect is reduced from 23 signals to only 4 active
signals with the LM4308 chipset easing flex interconnect de-
sign, size constraints and cost.
A low power sleep state entered when the PD* inputs are
driven low.
Features
■ ^{18-bit i80 CPU Display Interface}
■ ^{Supports up to 640 x 480 VGA formats}
■ ^{Differential SLVS Interface}
■ ^{Dual displays supported}
■ ^{WRITE and READ operations supported}
■ ^{Robust Differential Physical Layer}
■ ^{400mVpp differential signal swing}
■ ^{Internal 100 Ω Termination Resistor}
■ ^{Low Power Consumption}
■ ^{5-bit CRC for data integrity}
■ ^{Level translation between host and display}
■ ^{Low Power sleep state}
■ ^{3.3V Tolerant Master Clock Input regardless of V}_DDIO
■ ^{Fast Start Up Time - 1k CLK cycles}
■ ^{1.6V to 2.0V core / analog supply voltage}
■ ^{1.6V to 3.0V I/O supply voltage range}
System Benefits
■ ^{Small Interface}
■ ^{Low Power}
■ ^{Low EMI}
■ ^{Intrinsic Level Translation}
Typical Application Diagram
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