DS92LX2121 Datasheet, PDF (6/10 Pages) National Semiconductor (TI) – 10 - 50 MHz Channel Link III Serializer and Deserializer with Embedded Bi-Directional Control Channel

DS92LX2122 Deserializer Pin Descriptions
Pin Name Number of Pins
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
ROUT[20:0]
21
Outputs, LVCMOS Parallel data outputs.
PCLK
Pixel Clock Output Pin.
1
Output, LVCMOS Strobe edge set by RFB configuration. In SLEEP, outputs are controlled by
the OSS_SEL.
General Purpose Input (GPI)
GPI[3:0]
4
Input/Output, Digital
General-purpose pins individually configured as inputs; which are used to
control and respond to various commands.
SERIAL CONTROL BUS - I²C COMPATIBLE
SCL
SDA
M/S
1
Input/Output, Open Clock line for the serial control bus communication
Drain
SCL requires an external pull-up resistor to V_DDIO.
1
Input/Output, Open Data line for serial control bus communication
Drain
SDA requires an external pull-up resistor to V_DDIO.
I²C Master / Slave select
Input, LVCMOS w/
1
pull up
M/S = L, Master; device generates and drives the SCL clock line
M/S = H, Slave (default); device accepts SCL clock input
Continuous Address Decoder
CAD
1
Input, analog
Input pin to select the Slave Device Address.
Input is connect to external resistor divider to programmable Device ID
address (see Serial Control Bus Connection)
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB
1
Input, LVCMOS w/ ^{PDB = H, Receiver is enabled and is ON.}
pull down
PDB = L, Receiver is in Sleep (Power down mode). When the Receiver is in
the SLEEP state, the LVCMOS Outputs are in TRI-STATE, the PLL is
shutdown and IDD is minimized.
LOCK
LOCK Status Output Pin.
1
Output, LVCMOS ^{LOCK = H, PLL is Locked, outputs are active}
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL. May be used as Link Status.
Reserved.
RES
4
-
Pin 46: This pin MUST be tied LOW.
Pins 38, 39, 43: Leave pin open.
BIST MODE
BISTEN
BIST Enable Pin.
1
Input, LVCMOS w/ _{BISTEN = H, BIST Mode is enabled.}
pull down
BISTEN = L, BIST Mode is disabled.
PASS Output Pin for BIST mode.
PASS
PASS = H, ERROR FREE Transmission
1
Output, LVCOMS
PASS = L, one or more errors were detected in the received payload.
Leave Open if unused. Route to test point (pad) recommended.
Channel Link III INTERFACE
RIN+
1
Input/Output, CML Noninverting differential input, back channel output.
RIN-
1
Input/Output, CML Inverting differential input, back channel output.
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