DS92LX2121 Datasheet, PDF (4/10 Pages) National Semiconductor (TI) – 10 - 50 MHz Channel Link III Serializer and Deserializer with Embedded Bi-Directional Control Channel

DS92LX2121 Serializer Pin Descriptions
Pin Name Number of Pins
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
DIN[20:0]
21
Inputs, LVCMOS w/ Parallel data inputs.
pull down
PCLK
1
Input, LVCMOS w/ Pixel Clock Input Pin. Strobe edge set by TRFB configuration.
pull down
GENERAL PURPOSE OUTPUT (GPO)
GPO[3:0]
4
Output, Digital General-purpose pins individually configured as outputs; which are used to
control and respond to various commands.
SERIAL CONTROL BUS - I²C COMPATIBLE
SCL
SDA
M/S
1
Input/Output, Open Clock line for the serial control bus communication
Drain
SCL requires an external pull-up resistor to V_DDIO.
1
Input/Output, Open Data line for the serial control bus communication
Drain
SDA requires an external pull-up resistor to V_DDIO.
I²C Master / Slave select
Input, LVCMOS w/
1
pull down
M/S = L, Master (default)r; device generates and drives the SCL clock line
M/S = H, Slave; device accepts SCL clock input
CAD
Continuous Address Decoder
1
Input, analog
Input pin to select the Slave Device Address.
Input is connect to external resistor divider to programmable Device ID
address (see Serial Control Bus Connection).
CONTROL AND CONFIGURATION
PDB
Power down Mode Input Pin.
1
Input, LVCMOS w/ PDB = H, Transmitter is enabled and is ON.
pull down
PDB = L, Transmitter is in Sleep (Power Down). When the transmitter is in
the SLEEP state, the PLL is shutdown, and IDD is minimized.
RES
Input, LVCMOS w/ Reserved. This pin MUST be tied LOW.
2
pull down
Channel Link III INTERFACE
DOUT+
1
Input/Output, CML Non-inverting differential output, back-channel input.
DOUT-
1
Input/Output, CML Inverting differential output, back-channel input.
Power and Ground
VDDPLL
1
Power, Analog PLL Power, 1.8V ±5%
VDDT
1
Power, Analog Tx Analog Power, 1.8V ±5%
VDDCML
1
Power, Analog LVDS & BC Dr Power, 1.8V ±5%
VDDD
1
Power, Digital Digital Power, 1.8V ±5%
VDDIO
VSS
1
Power, Digital Power for input stage, The single-ended inputs are powered from V_DDIO.
-
Ground, DAP All VSS pads are down bonded to DAP. DAP must be grounded.
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