DS92LX1621 Datasheet, PDF (6/10 Pages) National Semiconductor (TI) – 10 - 50 MHz Channel Link III Serializer and Deserializer with Embedded Bi-Directional Control Channel

DS92LX1622 Deserializer Pin Descriptions
Pin Name Number of Pins
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
ROUT[13:0]
14
Outputs, LVCMOS Parallel data outputs.
HSYNC
1
Output, LVCMOS Horizontal SYNC Output, can be used as parallel data output 14
VSYNC
1
Output, LVCMOS Vertical SYNC Output, can be used as parallel data output 15
PCLK
Pixel Clock Output Pin.
1
Output, LVCMOS Strobe edge set by RFB configuration. In SLEEP, outputs are controlled by
the OSS_SEL.
General Purpose Input Output (GPIO)
ROUT[3:0] /
GPIO[5:2]
-
Input/Output, Digital
ROUT[3:0] general-purpose pins can be individually configured as either
inputs or outputs; used to control and respond to various commands.
GPIO[1:0]
2
Input/Output, Digital ^{General-purpose pins can be individually configured as either inputs or}
outputs; used to control and respond to various commands.
SERIAL CONTROL BUS - I²C COMPATIBLE
SCL
SDA
M/S
Clock line for the serial control bus communication
1
Input/Output, Digital _{SCL requires an external pull-up resistor to VDDIO.}
Input/Output, Open Data line for serial control bus communication
1
Drain
SDA requires an external pull-up resistor to V_DDIO.
I²C Master / Slave select
Input, LVCMOS w/
1
pull up
M/S = L, Master; device generates and drives the SCL clock line
M/S = H, Slave (default); device accepts SCL clock input
Continuous Address Decoder
CAD
1
Input, analog
Input pin to select the Slave Device Address.
Input is connect to external resistor divider to programmable Device ID
address (see Serial Control Bus Connection)
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB
1
Input, LVCMOS w/ ^{PDB = H, Receiver is enabled and is ON.}
pull down
PDB = L, Receiver is in Sleep (Power down mode). When the Receiver is in
the SLEEP state, the LVCMOS Outputs are in TRI-STATE, the PLL is
shutdown and IDD is minimized.
LOCK Status Output Pin.
LOCK
1
Output, LVCMOS ^{LOCK = H, PLL is Locked, outputs are active}
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL. May be used as Link Status.
Reserved.
RES
3
-
Pin 40: This pin MUST be tied LOW.
Pins 32,33: Leave pin open.
BIST MODE
BISTEN
BIST Enable Pin.
1
Input, LVCMOS w/
pull down
BISTEN = H, BIST Mode is enabled.
BISTEN = L, BIST Mode is disabled.
PASS Output Pin for BIST mode.
PASS
PASS = H, ERROR FREE Transmission
1
Output, LVCOMS
PASS = L, one or more errors were detected in the received payload.
Leave Open if unused. Route to test point (pad) recommended.
Channel Link III INTERFACE
RIN+
1
Input/Output, CML Noninverting differential input, back channel output.
RIN-
1
Input/Output, CML Inverting differential input, back channel output.
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