DS92LX1621 Datasheet, PDF (1/10 Pages) National Semiconductor (TI) – 10 - 50 MHz Channel Link III Serializer and Deserializer with Embedded Bi-Directional Control Channel

ADVANCE
DS92LX1621 / DS92LX1622 INFORMATION
June 1, 2010
10 - 50 MHz Channel Link III Serializer and Deserializer with
Embedded Bi-Directional Control Channel
General Description
The DS92LX1621/DS92LX1622 chipset offers a Channel
Link III interface with a high-speed forward channel and a full-
duplex control channel for data transmission over a single
differential pair. The Serializer/Deserializer pair is targeted for
direct connections between camera systems and Host Con-
troller/Frame Grabbers. The primary transport sends 16 bits
of image data over a single high-speed serial stream together
with a low latency bi-directional control channel transport that
supports I2C. Included with the 16-bit payload is a selectable
data integrity option for CRC (Cyclic Redundancy Check) or
parity bit to monitor transmission link errors. Using National’s
embedded clock technology allows transparent full-duplex
communication over a single differential pair, carrying asym-
metrical bi-directional control information without the depen-
dency of video blanking intervals. This single serial stream
simplifies transferring a wide data bus over PCB traces and
cable by eliminating the skew problems between parallel data
and clock paths. This significantly saves system cost by nar-
rowing data paths that in turn reduce cable width, connector
size and pins.
In addition, the Deserializer inputs provide equalization con-
trol to compensate for loss from the media over longer dis-
tances. Internal DC balanced encoding/decoding is used to
support AC-Coupled interconnects.
A sleep function provides a power-savings mode when the
high speed forward channel and embedded bi-directional
control channel are not needed.
The Serializer is offered in a 32-pin LLP package and Dese-
rializer is offered in a 40-pin LLP package.
Features
■ ^{Configurable data throughput}
— 12–bit (min) up to 600 Mbits/sec
— 16–bit (def) up to 800 Mbits/sec
— 18–bit (max) up to 900 Mbits/sec
■ ^{10 MHz to 50 MHz input clock support}
■ ^{Embedded clock with DC Balanced coding to support AC-}
coupled interconnects
■ ^{Capable to drive up to 10 meters shielded twisted-pair}
■ ^{Bi-directional control interface channel with I2C support}
■ ^{I2C interface for device configuration. Single-pin ID}
addressing
■ ^{16–bit data payload with CRC (Cyclic Redundancy Check)}
for checking data integrity with programmable data
transmission error detection and interrupt control
■ ^{Up to 6 Programmable GPIO's}
■ ^{AT-SPEED BIST diagnosis feature to validate link integrity}
■ ^{Individual power-down controls for both SER and DES}
■ ^{User-selectable clock edge for parallel data on both SER}
and DES
■ ^{Integrated termination resistors}
■ ^{1.8V- or 3.3V-compatible parallel bus interface}
■ ^{Single power supply at 1.8V}
■ ^{IEC 61000–4–2 ESD compliant}
■ ^{No reference clock required on Deserializer}
■ ^{Programmable Receive Equalization}
■ ^{LOCK output reporting pin to ensure link status}
■ ^{EMI/EMC Mitigation}
— DES Programmable Spread Spectrum (SSCG)
outputs
— DES Receiver Output Clock and Data Slew Rate Select
— DES Receiver staggered outputs
■ ^{Temperature range −40°C to +85°C}
■ ^{SER package: 32 pin LLP (5mm x 5mm)}
■ ^{DES package: 40 pin LLP (6mm x 6mm)}
Applications
■ ^{Industrial Displays, Touch Screens}
■ ^{Medical Imaging}
Typical Application Diagram
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