DS90C365A Datasheet, PDF (6/12 Pages) National Semiconductor (TI) – +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display Link-85 MHz

AC Timing Diagrams
FIGURE 1. “Worst Case” Test Pattern (Note 7)
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FIGURE 2. “16 Grayscale” Test Pattern - DS90C365A (Notes 8, 9, 10)
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Note 7: The worst case test pattern produces a maximum toggling of digital
circuits, LVDS I/O and LVCMOS/LVTTL I/O.
Note 8: The 16 grayscale test pattern tests device power consumption for a
“typical” LCD display pattern. The test pattern approximates signal switching
needed to produce groups of 16 vertical stripes across the display.
Note 9: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK
OUT).
Note 10: Recommended pin to signal mapping. Customer may choose to
define differently.
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FIGURE 3. DS90C365A (Transmitter) LVDS Output Load. 5pF is showed as board loading
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