DS90C365A Datasheet, PDF (10/12 Pages) National Semiconductor (TI) – +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display Link-85 MHz

Applications Information
The DS90C365A is backward compatible with the
DS90C365, DS90C363A, DS90C363 in TSSOP 48-lead
package, and it is a pin-for-pin replacements.
This device DS90C365A also features reduced variation of
the TCCD parameter which is important for dual pixel appli-
cations. (See AN-1084)
This device may also be used as a replacement for the
DS90CF563 (5V, 65MHz) and DS90CF561 (5V, 40MHz)
FPD-Link Transmitters with certain considerations/
modifications:
1. Change 5V power supply to 3.3V. Provide this 3.3V
supply to the V_CC, LVDS V_CC and PLL V_CC of the
transmitter.
2. The DS90C365A transmitter input and control inputs
accept 3.3V LVTTL/LVCMOS levels. They are not 5V
tolerant.
3. To implement a falling edge device for the DS90C365A,
the R_FB pin may be tied to ground OR left unconnected
(an internal pull-down resistor biases this pin low). Bias-
ing this pin to Vcc implements a rising edge device.
TRANSMITTER INPUT PINS
The TxIN and control input pins are compatible with LVC-
MOS and LVTTL levels. These pins are not 5V tolerant.
signal. The DS90C365A offers a more robust input sequenc-
ing feature where the input clock/data can be inserted after
the release of the PD signal. In the case where the clock/
data is stopped and reapplied, such as changing video mode
within Graphics Controller, it is not necessary to cycle the PD
signal. Asserting the PWR DOWN pin will effectively place
the device in reset and disable the PLL, enabling the LVDS
Transmitter into a power saving standby mode. However, it is
still generally a good practice to assert the PWR DOWN pin
or reset the LVDS transmitter whenever the clock/data is
stopped and reapplied but it is not mandatory for the
DS90C365A.
SPREAD SPECTRUM CLOCK SUPPORT
The DS90C365A can support Spread Spectrum Clocking
signal type inputs. The DS90C365A outputs will accurately
track Spread Spectrum Clock/Data inputs with modulation
frequencies of up to 100kHz (max.)with either center spread
of ±2.5% or down spread -5% deviations.
POWER SOURCES SEQUENCE
In typical applications, it is recommended to have V_CC, LVDS
V_CC and PLL V_CC from the same power source with three
separate de-coupling bypass capacitor groups. There is no
requirement on which VCC entering the device first.
TRANSMITTER INPUT CLOCK/DATA SEQUENCING
Unlike the DS90C365, DS90C(F)383A/363A, the
DS90C365A does not require any special requirement for
sequencing of the input clock/data and PD (PowerDown)
Pin Diagram for TSSOP Packages
DS90C365AMT
www.national.com
20100540
10