DP83858 Datasheet, PDF (6/37 Pages) National Semiconductor (TI) – 100 Mb/s TX/T4 Repeater Interface Controller (100RIC8™)

2.0 Pin Descriptions
2.1 Physical Layer Interface
Signal Name Type Active
Description
RXD[3:0]
I
— Receive Data: Nibble data inputs from each Physical layer chip. Up to 12 ports are sup-
ported.
Note: Input buffer has a weak pull-up.
RXE[7:0]
O, L high (low) Receive Enable: Asserted to the respective Physical Layer chip to enable its Receive
Data. These pins are either active high or active low depending on the polarity of RSM3
pin as shown below:
RXE[7:0] RSM3
Active High Unconnected or pulled high
Active Low Pulled down
RX_DV
I
high Receive Data Valid: Asserted High when valid data is present on RXD[3:0].
Note: To ensure that during idle, when 100PHYs TRI-STATE®, this signal is NOT inter-
preted as “logic one” by the repeater, a 1kΩ pull down resistor must be placed on this
pin. The location on this pull down should be between the repeater and the nearest tri-
stateable component to the repeater.
RX_ER
I
high Receive Error: The physical Layer asserts this signal high when it detects receive error.
When this signal is asserted, the 100PHY (TX or T4) device indicates the type of error
on RXD[3:0] as shown below. Note that this data is passed only to the Inter Repeater
Bus, and not onto the TX Bus:
RX_ER
RXD[3:0] Receive Error Condition
0
data
Normal data reception
1
0h
Symbol code violation
1
1h¹
Elasticity Buffer Over/Under-run
1
2h
Invalid Frame Termination
1
3h²
Reserved
1
4h²
10Mb Link Detected
1 _{The 100PHY must be configured with the Elasticity Buffer bypassed; hence this error}
code will never be generated.
2 _{These error codes will only appear when CRS from the 100PHY is not asserted. Since}
the DP83858 only enables a 100PHY when its CRS is asserted, these error codes will
never be passed through the chip.
Note: Input buffer has a weak pull-down.
RXC
I
— Receive Clock: Recovered clock from the Physical Layer device. RXD, RX_DV, and
RX_ER are generated from the falling edge of this clock.
Note: Input buffer has a weak pull-down.
CRS[7:0]
I
high Carrier Sense: Asynchronous carrier indication from the Physical Layer device.
TXE[7:0]
O, L high Transmit Enable: Enables corresponding port for transmitting data.
TX_RDY
O, L high Transmit Ready: Indicates when a transmit is in progress. Essentially, this signal is the
logical 'OR' of all TXEs.
TX_ER
O, M high Transmit Error: Asserted high when a code violation is requested to be transmitted.
TXD[3:0]
O, H high Transmit Data: Nibble data output to be transmitted by each Physical Layer device.
Note: A table showing pin type designation is given in section 2.5
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