DP83858 Datasheet, PDF (1/37 Pages) National Semiconductor (TI) – 100 Mb/s TX/T4 Repeater Interface Controller (100RIC8™)

June 1998
DP83858
100 Mb/s TX/T4 Repeater Interface Controller (100RIC8^™)
General Description
The DP83858 100 Mb/s TX/T4 Repeater Interface Control-
ler, known as 100RIC8, is designed specifically to meet the
needs of today's high speed Ethernet networking systems.
The DP83858 is fully compatible with the IEEE 802.3
repeater's clause 27. This device is targeted at low port
count managed and unmanaged repeater applications.
The DP83858 supports up to eight 100 Mb/s links with its
network interface ports. The 100RIC8 can be configured to
be used with either 100BASE-TX or 100BASE-T4 PHY
technologies. Larger repeaters may be constructed by
cascading DP83858s together using the built-in Inter
Repeater bus.
In conjunction with a DP83856 100 Mb/s Repeater Infor-
mation Base device, a DP83858 based repeater becomes
a managed entity that is compatible with IEEE 802.3u
(clause 30), collecting and providing an easy interface to
all the required network statistics.
Features
s IEEE 802.3u repeater and management compatible
s Supports Class II TX translational repeater and Class I
T4 repeater
s Supports 8 network connections (ports)
s Up to 31 repeater chips cascadable for larger hub appli-
cations--may use DP83858 in conjunction with DP83850
100RIC (12 ports per chip)
s Separate jabber and partition state machines for each
port
s Management interface to DP83856 allows all repeater
MIBs to be maintained
s Large per-port management counters - reduces man-
agement CPU overhead
s On-chip elasticity buffer for PHY signal re-timing to the
DP83858 clock source
s Serial register interface - reduces cost
s Physical layer device control/status access available via
the serial register interface
s Detects repeater identification errors
s 132 pin PQFP package
System Diagram
DP83858
100 Mb/s
Repeater Interface Controller
(100RIC8)
DP83856
100 Mb/s
Repeater Information Base
(100RIB)
Inter Repeater Bus
Management Bus
RX Enable [7..0]
MII
DP83840A
100 PHY
#0
100Mb/s
Ethernet
Ports
DP83223
100BASE-X
Transceiver
Port 0
DP83840A
100 PHY
#1
DP83223
100BASE-X
Transceiver
Port 1
DP83840A
100 PHY
#2
DP83223
100BASE-X
Transceiver
Port 2
(IR_COL, IR_DV)
DP83840A
100 PHY
#7
DP83223
100BASE-X
Transceiver
Port 7
Statistics
SRAM
Management
CPU
Program
Memory
Management
I/O Devices
Note: The above system diagram depicts the repeater configured in 100BASE-TX mode.
FAST^® is a registered trademark of Fairchild Semiconductor Corporation.
TRI-STATE^® is a registered trademark of National Semiconductor Corporation.
100RIC^™ is a trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
http:\\www.national.com