DAC128S085 Datasheet, PDF (6/24 Pages) National Semiconductor (TI) – 12-Bit Micro Power OCTAL Digital-to-Analog Converter with Rail-to-Rail Outputs

Symbol
Parameter
Conditions
f_SCLK = 30 MHz
output unloaded
P_N
Total Power Consumption (output
unloaded)
f_SCLK = 0
output unloaded
V_A = 2.7V
to 3.6V
V_A = 4.5V
to 5.5V
V_A = 2.7V
to 3.6V
V_A = 4.5V
to 5.5V
f_SCLK = 30 MHz, SYNC =
V_A = 2.7V
to 3.6V
Total Power Consumption in all PD
V_A and D_IN = 0V after PD
mode loaded
V_A = 4.5V
to 5.5V
P_PD
Modes,
(Note 9)
f_SCLK = 0, SYNC = V_A and
V_A = 2.7V
to 3.6V
D_IN = 0V after PD mode
loaded
V_A = 4.5V
to 5.5V
Typical
1.95
Limits
(Note 8)
3.0
Units
(Limits)
mW (max)
4.85
7.0
mW (max)
1.68
mW
3.80
mW
0.6
5.4
µW (max)
2.5
16.5
µW (max)
0.3
3.6
µW (max)
1
11
µW (max)
A.C. and Timing Characteristics
The following specifications apply for V_A = +2.7V to +5.5V, V_REF1,2 = V_A, C_L = 200 pF to GND, f_SCLK = 30 MHz, input code range
48 to 4047. Boldface limits apply for T_MIN ≤ T_A ≤ T_MAX and all other limits are at T_A = 25°C, unless otherwise specified.
Symbol
Parameter
Conductions
Typical
Limits
(Note 8)
Units
(Limits)
f_SCLK
t_s
SR
SCLK Frequency
Output Voltage Settling Time
(Note 9)
Output Slew Rate
400h to C00h code change
R_L = 2kΩ, C_L = 200 pF
40
30
MHz (max)
6
8.5
µs (max)
1
V/µs
GI Glitch Impulse
Code change from 800h to 7FFh
40
nV-sec
DF Digital Feedthrough
0.5
nV-sec
DC Digital Crosstalk
0.5
nV-sec
CROSS DAC-to-DAC Crosstalk
1
nV-sec
MBW Multiplying Bandwidth
V_REF1,2 = 2.5V ± 2Vpp
360
THD+N
Total Harmonic Distortion Plus Noise
V_REF1,2 = 2.5V ± 0.5Vpp
100Hz < f_IN < 20kHz
−80
ONSD Output Noise Spectral Density
DAC Code = 800h, 10kHz
40
kHz
dB
nV/sqrt(Hz)
ON Output Noise
BW = 30kHz
14
µV
t_WU Wake-Up Time
1/f_SCLK
t_CH
t_CL
t_SS
t_DS
SCLK Cycle Time
SCLK High time
SCLK Low Time
SYNC Set-up Time prior to SCLK
Falling Edge
Data Set-Up Time prior to SCLK
Falling Edge
V_A = 3V
V_A = 5V
3
µsec
20
µsec
25
33
ns (min)
7
10
ns (min)
7
10
ns (min)
3
10
ns (min)
1 / f_SCLK - 3 ns (max)
1.0
2.5
ns (min)
t_DH
Data Hold Time after SCLK Falling
Edge
1.0
2.5
ns (min)
t_SH
t_SYNC
SYNC Hold Time after the 16th falling
edge of SCLK
SYNC High Time
0
3
ns (min)
1 / f_SCLK - 3 ns (max)
5
15
ns (min)
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