DP83640 Datasheet, PDF (59/114 Pages) National Semiconductor (TI) – Precision PHYTER - IEEE 1588 Precision Time Protocol Transceiver

14.2.4 RMII and Bypass Register (RBR)
This register configures the RMII/MII Interface Mode of operation. This register controls selecting MII, RMII, or Single Clock MII
mode for Receive or Transmit. In addition, several additional bits are included to allow datapath selection for Transmit and Receive
in multiport applications.
Bit
Bit Name
15
RESERVED
14
RMII_MASTER
13
DIS_TX_OPT
12:9
RESERVED
8
PMD_LOOP
7
SCMII_RX
6
SCMII_TX
5
RMII_MODE
4
RMII_REV1_0
3
RX_OVF_STS
TABLE 30. RMII and Bypass Register (RBR), address 0x17
Default
0, RW
Strap, RW
0, RW
0000, RW
0, RW
0, RW
0, RW
Strap, RW
0, RW
0, RO
Description
RESERVED: Must be 0.
RMII Master Mode:
Setting this bit allows the core to use a 25 MHz input reference clock and generate
its own 50 MHz RMII reference clock. The generated RMII reference clock will
also be used by the attached MAC.
1 = RMII Master Mode (25 MHz input reference)
0 = RMII Slave Mode (50 MHz input reference)
Note: Due to clock muxing and divider operation, this bit should normally only be
reconfigured via the strap option.
Disable RMII TX Latency Optimization:
Normally the RMII Transmitter will minimize the transmit latency by realigning the
transmit clock with the reference clock phase at the start of a packet transmission.
Setting this bit will disable phase realignment and ensure that IDLE bits will
always be sent in multiples of the symbol size. This will result in a larger
uncertainty in RMII transmit latency.
RESERVED: Must be 0.
PMD Loopback:
0 = Normal Operation.
1 = Remote (PMD) Loopback.
Setting this bit will cause the device to Loopback data received from the Physical
Layer. The loopback is done prior to the MII or RMII interface. Data received at
the internal MII or RMII interface will be applied to the transmitter. This mode
should only be used if RMII mode or Single Clock MII mode is enabled.
Single Clock RX MII Mode:
0 = Standard MII mode.
1 = Single Clock RX MII Mode.
Setting this bit will cause the device to generate receive data (RX_DV, RX_ER,
RXD[3:0]) synchronous to the X1 Reference clock. RX_CLK is not used in this
mode. This mode uses the RMII elasticity buffer to tolerate variations in clock
frequencies. This bit cannot be set if RMII_MODE is set to a 1.
Single Clock TX MII Mode:
0 = Standard MII mode.
1 = Single Clock TX MII Mode.
Setting this bit will cause the device to sample transmit data (TX_EN, TXD[3:0])
synchronous to the X1 Reference clock. TX_CLK is not used in this mode. This
bit cannot be set if RMII_MODE is set to a 1.
Reduced MII Mode:
0 = Standard MII Mode.
1 = Reduced MII Mode.
Reduced MII Revision 1.0:
This bit modifies how CRS_DV is generated.
0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet to indicate
deassertion of CRS.
1 = (RMII revision 1.0) CRS_DV will remain asserted until final data is transferred.
CRS_DV will not toggle at the end of a packet.
RX FIFO Over Flow Status:
0 = Normal.
1 = Overflow detected.
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