PC87570 Datasheet, PDF (58/168 Pages) National Semiconductor (TI) – PC87570 Keyboard and Power Management Controller

Host Bus Interface (HBI)
interrupt is sent at that time. If the CR16A interrupt on output
buffer empty is enabled (OBECIE in the HICTRL Register is
1), writing to HIKDO de-asserts it (low).
7
6
5
4
3
2
1
0
MSB
Keyboard Channel DBBOUT Data
LSB
5.12.10 Host Interface Mouse Data Out Buffer Register
(HIMDO)
The HIMDO Register is a byte wide, write only register. It al-
lows the CR16A firmware to write to the DBBOUT register,
while setting OBF in the HIKMST Register. If enabled,
IRQ12 interrupt is sent at that time. If the CR16A interrupt
on output buffer empty is enabled (OBECIE in the HICTRL
Register is 1), writing to HIMDO de-asserts it (low).
7
6
5
4
3
2
1
0
MSB
Mouse Channel DBBOUT Data
LSB
5.12.11 Host Interface KBC Data In Buffer Register
(HIKMDI)
The HIKMDI Register is a byte wide, read only register. It al-
lows the CR16A firmware to read from the DBBIN Register,
while clearing IBF in the HIKMST Register. If the CR16A in-
terrupt on IBF is enabled (IBFCIE in the HICTRL Register is
1), reading from HIKMDI de-asserts it (low).
7
6
5
4
3
2
1
0
MSB
KBC Channel DBBIN Data
LSB
5.12.12 Host Interface PM Port Status Register (HIPMST)
The HIPMST Register is a byte wide, read/write register. It
provides the status of the host interface PM channel buffer
registers (DBBIN and DBBOUT) and a means for the
PC87570 to send data to the host status bits. This register
is read by a host read operation from address 66h. HIPMST
is cleared (00h) on reset.
7
6
5
4
3
2
1
0
ST3 ST2 ST1 ST0 A2 F0 IBF OBF
Bit 0 - Output Buffer Full (OBF)
This bit is a read only bit and is ignored when writing to
this register.
0: Host reads from the output buffer (62h)
1: PM channel’s DBBOUT is written by the CR16A
(writing to the HIPMDO Register)
Bit 1 - Input Buffer Full (IBF)
This bit is a read only bit and is ignored when writing to
this register.
0: CR16A core reads from the PM input buffer (HIPM-
DI Register)
1: PM channel’s DBBIN is written by the host (writing
to either address 62h or address 66h)
Bit 2 - Flag 0 (F0)
A general-purpose flag that can be set or cleared by the
CR16A firmware.
Bit 3 - A2 Address (A2)
Holds the value of the A2 line in the last write operation
of the host to the PM channel’s input buffer (indicates A2
value during write to address 62h or 66h). This bit is a
read only bit and is ignored when writing to this register.
Bits 7-4 - Status Bits 0-3 (ST0-3)
Four general-purpose flags that can be set or cleared by
the CR16A firmware.
5.12.13 Host Interface PM Data Out Buffer Register (HIPMDO)
The HIPMDO Register is a byte wide, write only register. It al-
lows the CR16A firmware to write to the PM port DBBOUT
Register, while setting OBF in the HIPMST Register. If en-
abled, IRQ11 interrupt is sent at that time. If the CR16A inter-
rupt on PM port output buffer empty is enabled (PMECIE in the
HICTRL Register is1), writing to HIPMDO de-asserts it (low).
7
6
5
4
3
2
1
0
MSB
PM Channel DBOUT Data
LSB
5.12.14 Host Interface PM Data In Buffer Register (HIPMDI)
The HIPMDI Register is a byte wide, read only register. It al-
lows the CR16A firmware to read to the PM port DBBIN
Register, while clearing IBF in the HIPMST Register. If the
CR16A interrupt on power Host Bus Interface and SIB Bus
Controller management port IBF is enabled (PMICIE in the
HICTRL Register is1), reading from HIPMDI de-asserts it
(low).
7
6
5
4
3
2
1
0
MSB
PM Channel DBBIN Data
LSB
5.13 HOST CHANNEL CONFIGURATION
The PC87570’s host channel is configurable using a moth-
erboard PnP protocol. The default configuration is set on re-
set, and the host can change it through this protocol.
5.13.1 Chip Base Address Initial Setting
The motherboard PnP protocol described in this section is
used for changing the configuration registers addresses.
This protocol must be used after reset to enable access to
the configuration registers.
While the PnP protocol is in process, CPU interrupts must
be disabled.
1. On reset, the chip writes a value of 6Ah to the 8-bit Lin-
ear Feedback Shift Register (LFSR). See Figure 5-6.
The feedback taps (values) for this shift register are tak-
en from bits 1 and 0 of the LFSR Register.
2. Use software to write an initiation key, to a single write-
only I/O port, at addresses 0279h, 03BDh, 03F0h or an
address defined by HCFGBAH and HCFGBAL Regis-
ters (if enabled).
Addresses 0279h, 03BDh and 03F0h do not conflict
with any already defined base addresses of ISA func-
tions. All write operations should be to the same I/O
port. In legacy devices, these same ports are read only.
The HCFGBAH and HCFGBA Register pair is updated
by the CR16A firmware after power-up or WATCHDOG
reset. On power-up it is undefined, and the firmware
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