DP83952 Datasheet, PDF (51/90 Pages) National Semiconductor (TI) – Repeater Interface Controller with Security Features (RIC II)

7 0 Port Block Functions (Continued)
7 5 LOCAL PORTS AND INTER-RIC BUS DATA FIELD CONTENTS
SME
ESA
EDA
Source
Address
of Packet
0
X
X
X
0
X
Match
0
Match
1
Mismatch
1
Mismatch
Match
Match
1
0
Mismatch
Match
1
Match
Mismatch
Note SME Security Mode bit in the Port Security Configuration Register (PSCR)
ESA Source Address Security bit in the PSCR register
EDA Destination Address Security bit in the PSCR register
Destination
Address
of Packet
X
X
Match
Mismatch
Match
Mismatch
Match
Mismatch
X
Match
Mismatch
X
Transmitting
Ports
Repeat
Repeat
Repeat
Random
Repeat
Random
Repeat
Repeat
Random
Repeat
Random
Random
Inter-RIC
Bus
Repeat
Repeat
Repeat
Repeat
Repeat
Repeat
Repeat
Repeat
Random
Repeat
Repeat
Random
8 0 RIC II Registers
RIC II REGISTER ADDRESS MAP
The RIC II’s registers may be accessed by applying the re-
quired address to the five Register Address (RA(4 0)) input
pins Pin RA4 makes the selection between the upper and
lower halves of the register array The lower half of the reg-
ister map consists of 16 registers
1 RIC II Real Time Status and Configuration register
13 Port Real Time Status registers
1 RIC II Configuration register
1 Real Time Interrupt Status register
These registers may be directly accessed at any time via
the RA(4 0) pins (RA4 e 0)
The upper half of the register map (RA4 e 1) is organized
as 15 pages of registers These pages include registers for
port security configuration (global and on a per port basis)
event count registers port CAM and shared CAM locations
CAM location mask registers etc See Memory Map and
Register Description sections for details
Register access within these pages is performed using the
RA(4 0) pins (RA4 e 1) Page switching is performed by
writing to the Page Selection bits (PSEL3 2 1 and 0) These
bits are found in the Page Select Register located at ad-
dress 10 hex on each page of the upper half of the register
array At power on these bits default to 0 Hex i e page
zero
On the RIC II the following registers have been added mod-
ified from the RIC registers
1 Page Select Register
2 ECIMR-2 register added to page (0)
3 GSR register added to page (0)
4 Upper and Lower EIR registers added to page (1)
5 Added all registers on pages (4) – (15)
6 Modification Option for Management Packet Status Reg-
ister 5 (PSR5) on the Management Bus
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