DP83952 Datasheet, PDF (1/90 Pages) National Semiconductor (TI) – Repeater Interface Controller with Security Features (RIC II)

PRELIMINARY
September 1995
DP83952
Repeater Interface Controller with
Security Features (RIC^TM II)
General Description
The DP83952 RIC II Repeater Interface Controller is an
‘‘Enhanced’’ version of the DP83950 RIC RIC II is fully
backward pin and functional compatible with the RIC The
DP83952 RIC II has the same basic architecture as the RIC
with additional feature enhancements RIC II provides addi-
tional network security options additional statistics for re-
peater activities and a faster processor interface When
RIC II is used in a ‘‘non-secure’’ mode it functions in the
same manner as the DP83950 RIC When RIC II is used in a
‘‘secure’’ mode it restricts unauthorized nodes from intrud-
ing and or eavesdropping into the network The RIC II uti-
lizes internal CAMs to store compare addresses of valid
nodes when network security is desired
RIC II implements the IEEE 802 3 multiport repeater unit
specifications It is fully compliant with the 802 3 repeater
specification for the repeater segment partition and jabber
lockup protection state machines (Continued)
Features
Y _{Compliant with the IEEE 802 3 Repeater Specification}
Y _{13 network connections (ports) per chip}
Y _{Selectable on-chip twisted-pair transceivers}
Y _{Cascadable for large hub applications}
Y _{Compatible with AUI compliant transceivers}
Y _{On-chip Elasticity Buffer Manchester encoder and}
decoder
Y _{Separate Partition state machines for each port}
Y _{Compatible with 802 3k Hub Management requirements}
Y _{Provides port status information for LED displays in-}
cluding receive collision partition link status and jab-
ber
Y _{Power-up configuration options}
Repeater and Partition Specifications Transceiver Inter-
face Status Display Processor Operations
Y _{Simple processor interface for repeater management}
and port disable
Y _{On-chip Event Counters and Event Flag Arrays}
Y _{Serial Management Bus Interface to combine packet}
and repeater status information
Y _{CMOS process for low power dissipation}
Y _{Single 5V supply}
Security Features
Y _{Power-up configuration options}
Y _{Prevents unauthorized eavesdropping and or intrusion}
on a per port basis
Y _{58 on-chip CAMs (Content Addressable Memory) allow}
storage of acceptable addresses
Y _{Learn mode automatically records addresses of at-}
tached nodes
1 0 System Diagram
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C1995 National Semiconductor Corporation TL F 12499
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