LP3945 Datasheet, PDF (5/15 Pages) National Semiconductor (TI) – Battery Charge Management System

Electrical Characteristics (Continued)
Unless otherwise noted, V_CHG-IN = 5V, V_BATT = 4V, C_CHG-IN = 1µF, C_BATT = 10µF. Typical values and limits appearing in nor-
mal type apply for T_J = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation,
T_J = −40˚C to +85˚C. (Notes 6, 7, 8)
Symbol
Parameter
Conditions
Typical
Limit
Min
Max
Units
BATTERY CHARGER — Li ION MODE (MODE = LOW)
Restart Threshold Voltage
V_BATT Falling, Transition from
3.9
3.77
4.02
(For 4.1V Cell)
EOC, to Pre-Qualification State
V_BAT-RST
Restart Threshold Voltage
V_BATT Falling, Transition from
4.00
3.86
4.12
V
(For 4.2V Cell)
EOC, to Pre-Qualification State
R_SENSE
Internal Current Sense
Resistance
Internal Current Sense Resistor
Load Current
(Note 7)
(Note 7)
120
mΩ
1.2
A
ICHG_MON
Diff-Amp Output
t_EOC
Time to EOC State
I_CHG = 50 mA
I_CHG = 500 mA
I_CHG = 950 mA
0˚C to +85˚C (Note 7)
−40˚C to +85˚C (Note 7)
0.583
1.333
V
2.090
5.625
4.78
6.42
Hrs
5.625
4.5
6.75
BATTERY CHARGER — NI-MH MODE (MODE = HIGH, LP3945 ONLY)
(Charging Current Decreases to
V_BATT-MAX Battery Over Voltage Protection 0 mA when V_BATT is above this
5.4
5.292
5.508
V
Voltage), V_CHG-IN = 5.6V
LDO MODE (BIPB=HIGH)
V_OUT
Output Voltage Regulation
I_LOAD=50mA
I_LOAD=950mA
4.10
4.06
V
LOGIC LEVELS
V_IL
Low Level Input Voltage
EN
V_IH
High Level Input Voltage
EN
EN = LOW
I_IL
Enable Pin Input Current
EN = HIGH
0.4
V
2.0
V
−10
+10
µA
−5
+5
Electrical Characteristics, I²C Interface (LP3945 Only)
Unless otherwise noted, V_CHG-IN = 5V, V_BATT = 4V. Typical values and limits appearing in normal type apply for T_J = 25˚C.
Limits appearing in boldface type apply over the entire junction temperature range for operation, T_J = −40˚C to +85˚C. (Notes
6, 7, 8)
Symbol
Parameter
Conditions
Typical
Limit
Min
Max
Units
V_IL
V_IH
V_OL
V_HYS
F_CLK
t_HOLD
Low Level Input Voltage
High Level Input Voltage
Low Level Output Voltage
Schmitt Trigger Input Hysteresis
Clock Frequency
Hold Time Repeated START
Condition
SDA & SCL
SDA & SCL
SDA & SCL
SDA & SCL
(Note 7)
0.4
0.3 V_DD
V
0.7 V_DD V_DD +0.5
V
0
0.2 V_DD
V
0.1 V_DD
V
400
kHz
0.6
µs
t_CLK-LP
t_CLK-HP
t_SU
CLK Low Period
CLK High Period
Set-up Time Repeated START
Condition
(Note 7)
(Note 7)
(Note 7)
1.3
µs
0.6
µs
0.6
µs
t_DATA-HOLD
t_DATA-SU
t_SU
Data Hold Time
Data Set-up Time
Set-up Time for STOP Condition
(Note 7)
(Note 7)
(Note 7)
300
ns
100
ns
0.6
µs
5
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