LMH6515 Datasheet, PDF (5/18 Pages) National Semiconductor (TI) – 600 MHz, Digital Controlled, Variable Gain Amplifier

Pin Descriptions
Pin Number
Analog I/O
6
Symbol
IN+
7
IN−
15
OUT−
14
OUT+
16
LOAD−
13
LOAD+
Power
3
5,8
V_CC
GND
Digital Inputs
1,12,11,
10,9
2
GAIN_0 to
GAIN_4
LATCH
4
NC
Description
Non-inverting analog input. Internally biased to 1.4V. Input voltage should not exceed
V_CC or go below GND by more than 0.5V.
Inverting analog input. Internally biased to 1.4V. Input voltage should not exceed V_CC or
go below GND by more than 0.5V. If using amplifier single ended this input should be
capacitively coupled to ground.
Open collector inverting output. This pin is an output that also requires a power source.
This pin should be connected to 5V through either an RF choke or an appropriately sized
inductor that can form part of a filter. See application section for details.
Open collector non-inverting output. This pin is an output that also requires a power
source. This pin should be connected to 5V through either an RF choke or an
appropriately sized inductor that can form part of a filter. See application section for
details.
Internal 200Ω resistor connection to pin 15. This pin can be left floating for higher gain
or shorted to pin 13 for lower gain and lower effective output impedance. See application
section for details.
Internal 200Ω resistor connection to pin 14. This pin can be left floating for higher gain
or shorted to pin 16 for lower gain and lower effective output impedance. See application
section for details.
5V power supply pin. Use ceramic, low ESR bypass capacitors. This pin powers
everything except the output stage.
Ground pins. Connect to low impedance ground plane. All pin voltages are specified with
respect to the voltage on these pins. The exposed thermal pad is also a ground
connection.
Gain setting pins. See above table for gain step sizes for each pin. These pins are 3.3V
CMOS logic compatible. 5V inputs may cause damage.
This pin controls the function of the gain setting pins mentioned above. With LATCH in
the logic HIGH state the gain is fixed and will not change. With the LATCH in the logic
LOW state the gain is set by the state of the gain control pins. Any changes in gain made
with the LATCH pin in the LOW state will take effect immediately. This pin is 3.3V CMOS
logic compatible. 5V inputs may cause damage.
This pin is not connected. It can be grounded or left floating.
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