LMH6515 Datasheet, PDF (3/18 Pages) National Semiconductor (TI) – 600 MHz, Digital Controlled, Variable Gain Amplifier

Symbol
Parameter
Conditions
Differential Output Impedance
Low Gain Option
High Gain Option
Internal Load Resistors
Between Pins 13, 14 and Pins 15, 16
Input Signal Level (AC Coupled) Max Gain, V_O = 2 V_PP, R_L = 1 kΩ
Maximum Differential Input Signal AC Coupled
Input Common Mode Voltage
Self Biased
V_OS
CMRR
PSRR
Input Common Mode Voltage
Range
Minimum Input Voltage
Maximum Input Voltage
Maximum Differential Output
Voltage Swing
Output Offset Voltage
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Driven Externally
DC
DC
V_CC = 5V, Output Common Mode = 5V
All Gain Settings
Gain Parameters
Maximum Gain
Minimum Gain
Gain Step Size
Gain Step Error
Cumulative Gain Step Error
DC, Internal R_L = 200Ω,
External R_L = 1280Ω
DC, Internal R_L = 200Ω,
External R_L = 1280Ω
DC
DC
f = 150 MHz
DC, Gain Step 31 to Gain Step 0
Gain Step Switching Time
Digital Inputs/Timing
Logic Compatibility
VIL
Logic Input Low Voltage
VIH
Logic Input High Voltage
IIH
Logic Input High Input Current
TSU
Setup Time
THOLD Hold Time
TPW
Minimum Latch Pulse Width
Power Requirements
ICC
Total Supply Current
Amplifier Supply Current
CMOS Logic
V_OUT = 0V Differential, V_OUT Common
Mode = 5V
Pin 3 Only
Output Stage Bias Currents
Pins 13, 14 and Pins 15, 16;
V_OUT Common Mode = 5 V
Min
(Note 6)
330
325
165
160
Typ
(Note 5)
187
370
187
126
Max
(Note 6)
410
415
210
235
5.6
1.3
1.4
1.5
1.1
1.7
0.9 to 2.0
0
3.3
5.5
30
85
63
83
61
23.9
24.2
24.6
23.4
24.8
−7.2
−6.9
−6.5
−7.7
−6.4
1.0
0.02
0.07
−0.1
0.05
0.3
−0.2
0.4
5
3.3
0.8
2.0
32
40
3
3
10
107
124
134
56
66
74
48
58
60
Units
Ω
Ω
mV_PP
V_PP
V
V
V
V
V_PP
mV
dB
dB
dB
dB
dB
dB
dB
ns
V
V
V
μA
ns
ns
ns
mA
mA
mA
3
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