LMC567 Datasheet, PDF (5/7 Pages) National Semiconductor (TI) – Low Power Tone Decoder

Applications Information (refer to Block
Diagram) (Continued)
SUPPLY DECOUPLING
The decoupling of supply pin 4 becomes more critical at high
supply voltages with high operating frequencies, requiring
C4 to be placed as close as possible to pin 4.
INPUT PIN
The input pin 3 is internally ground-referenced with a nomi-
nal 40 kΩ resistor. Signals which are already centered on 0V
may be directly coupled to pin 3; however, any d.c. potential
must be isolated via a coupling capacitor. Inputs of multiple
LMC567 devices can be paralleled without individual d.c.
isolation.
LOOP FILTER
Pin 2 is the combined output of the phase detector and con-
trol input of the VCO for the phase-locked loop (PLL). Ca-
pacitor C2 in conjunction with the nominal 80 kΩ pin 2 inter-
nal resistance forms the loop filter.
For small values of C2, the PLL will have a fast acquisition
time and the pull-in range will be set by the built in VCO fre-
quency stops, which also determine the largest detection
bandwidth (LDBW). Increasing C2 results in improved noise
immunity at the expense of acquisition time, and the pull-in
range will begin to become narrower than the LDBW (see
Bandwidth as a Function of C2 curve). However, the maxi-
mum hold-in range will always equal the LDBW.
OUTPUT FILTER
Pin 1 is the output of a negative-going amplitude detector
which has a nominal 0 signal output of 7/9 V_s. When the PLL
is locked to the input, an increase in signal level causes the
detector output to move negative. When pin 1 reaches
2/3 V_s the output is activated (see OUTPUT PIN).
Capacitor C1 in conjunction with the nominal 40 kΩ pin 1 in-
ternal resistance forms the output filter. The size of C1 is a
tradeoff between slew rate and carrier ripple at the output
comparator. Low values of C1 produce the least delay be-
tween the input and output for tone burst applications, while
larger values of C1 improve noise immunity.
Pin 1 also provides a means for shifting the input threshold
higher or lower by connecting an external resistor to supply
or ground. However, reducing the threshold using this tech-
nique increases sensitivity to pin 1 carrier ripple and also re-
sults in more part to part threshold variation.
OUTPUT PIN
The output at pin 8 is an N-channel FET switch to ground
which is activated when the PLL is locked and the input tone
is of sufficient amplitude to cause pin 1 to fall below 2/3 V_s.
Apart from the obvious current component due to the exter-
nal pin 8 load resistor, no additional supply current is re-
quired to activate the switch. The on resistance of the switch
is inversely proportional to supply; thus the “sat” voltage for
a given output current will increase at lower supplies.
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