DS90LV004 Datasheet, PDF (5/7 Pages) National Semiconductor (TI) – 4-Channel LVDS Buffer/Repeater with Pre-Emphasis

Feature Descriptions
INTERNAL TERMINATIONS
The DS90LV004 has integrated termination resistors on both
the input and outputs. The inputs have a 100Ω resistor
across the differential pair, placing the receiver termination
as close as possible to the input stage of the device. The
LVDS outputs also contain an integrated 100Ω ohm termi-
nation resistor, this resistor is used to reduce the effects of
Near End Crosstalk (NEXT) and does not take the place of
the 100 ohm termination at the inputs to the receiving device.
The integrated terminations improve signal integrity and de-
crease the external component count resulting in space
savings.
OUTPUT CHARACTERISTICS
The output characteristics of the DS90LV004 have been
optimized for point-to-point backplane and cable applica-
tions, and are not intended for multipoint or multidrop signal-
ing.
POWERDOWN MODE
The PWDN input activates a hardware powerdown mode.
When the powerdown mode is active (PWDN=L), all input
and output buffers and internal bias circuitry are powered off
and disabled. Outputs are tri-stated in powerdown mode.
When exiting powerdown mode, there is a delay associated
with turning on bandgap references and input/output buffer
circuits as indicated in the LVDS Output Switching Charac-
teristics
PRE-EMPHASIS
Pre-emphasis dramatically reduces ISI jitter from long or
lossy transmission media. Two pins are used to select the
pre-emphasis level for all outputs: off, low, medium, or high.
Pre-emphasis Control Selection Table
PEM1
0
0
1
1
PEM0
0
1
0
1
Pre-Emphasis
Off
Low
Medium
High
INPUT FAILSAFE BIASING
External pull up and pull down resistors may be used to
provide enough of an offset to enable an input failsafe under
open-circuit conditions. This configuration ties the positive
LVDS input pin to V_DD thru a pull up resistor and the negative
LVDS input pin is tied to GND by a pull down resistor. The
pull up and pull down resistors should be in the 5kΩ to 15kΩ
range to minimize loading and waveform distortion to the
driver. The common-mode bias point ideally should be set to
approximately 1.2V (less than 1.75V) to be compatible with
the internal circuitry. Please refer to application note AN-
1194 “Failsafe Biasing of LVDS Interfaces” for more informa-
tion.
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