DS90LV004 Datasheet, PDF (2/7 Pages) National Semiconductor (TI) – 4-Channel LVDS Buffer/Repeater with Pre-Emphasis

Block and Connection Diagrams
20146601
DS90LV004 Block Diagram
20146602
TQFP Pinout - Top View
Pin Descriptions
Pin
TQFP Pin
Name
Number
DIFFERENTIAL INPUTS
IN0+
13
IN0−
14
IN1+
15
IN1−
16
IN2+
19
IN2−
20
IN3+
21
IN3−
22
DIFFERENTIAL OUTPUTS
OUT0+
48
OUT0−
47
OUT1+
46
OUT1−
45
OUT2+
42
OUT2−
41
OUT3+
40
OUT3-
39
DIGITAL CONTROL INTERFACE
PWDN
12
PEM0
1
PEM1
2
POWER
V_DD
3, 4, 5, 7, 10, 11, 27, 28, 29,
32, 33, 34
GND
8, 9, 17, 18, 23, 24, 25, 26,
37, 38, 43, 44
N/C
6, 30, 31, 35, 36
I/O, Type
Description
I, LVDS Channel 0 inverting and non-inverting differential inputs.
I, LVDS Channel 1 inverting and non-inverting differential inputs.
I, LVDS Channel 2 inverting and non-inverting differential inputs.
I, LVDS Channel 3 inverting and non-inverting differential inputs.
O, LVDS Channel 0 inverting and non-inverting differential outputs. (Note 1)
O, LVDS Channel 1 inverting and non-inverting differential outputs. (Note 1)
O, LVDS Channel 2 inverting and non-inverting differential outputs. (Note 1)
O, LVDS Channel 3 inverting and non-inverting differential outputs. (Note 1)
I, LVTTL A logic low at PWDN activates the hardware power down mode.
I, LVTTL Pre-emphasis Control Inputs (affects all Channels)
I, Power V_DD = 3.3V, ±5%
I, Power Ground reference for LVDS and CMOS circuitry.
No Connect
Note 1: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS90LV004 device have been optimized for
point-to-point backplane and cable applications.
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