DS90CF561 Datasheet, PDF (5/12 Pages) National Semiconductor (TI) – LVDS 18-Bit Color Flat Panel Display (FPD) Link

Transmitter Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
TCCD
TPLLS
TPDD
Parameter
TxCLK IN to TxCLK OUT Delay @ 25˚C,
V_CC = 5.0V (Figure 9)
Transmitter Phase Lock Loop Set (Figure 11)
Transmitter Powerdown Delay (Figure 15)
Note 5: This limit based on bench characterization.
Min Typ Max Units
5
9.7
ns
10
ms
100
ns
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
CLHT
CHLT
RCOP
RSKM
Parameter
CMOS/TTL Low-to-High Transition Time (Figure 4)
CMOS/TTL High-to-Low Transition Time (Figure 4)
RxCLK OUT Period (Figure 8)
Receiver Skew Margin (Note 6). V_CC = 5V, T_A = 25˚C (Figure 18)
RCOH RxCLK OUT High Time (Figure 8)
RCOL RxCLK OUT Low Time (Figure 8)
RSRC RxOUT Setup to RxCLK OUT (Figure 8)
RHRC RxOUT Hold to RxCLK OUT (Figure 8)
RCCD
RPLLS
RPDD
RxCLK IN to RxCLK OUT Delay @ 25˚C,
V_CC = 5.0V (Figure 10)
Receiver Phase Lock Loop Set (Figure 12)
Receiver Powerdown Delay (Figure 16)
f = 20 MHz
f = 40 MHz
f = 20 MHz
f = 40 MHz
f = 20 MHz
f = 40 MHz
f = 20 MHz
f = 40 MHz
f = 20 MHz
f = 40 MHz
Min Typ
3.5
2.7
25
T
1.1
700
21.5
10.5
19
6
14
4.5
16
6.5
7.6
Max Units
6.5
ns
6.5
ns
50
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
11.9 ns
10
ms
1
µs
Note 6: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter output skew(TCCS)
and the setup and hold time (internal data sampling window), allowing LVDS cable skew dependent on type/length and source clock(TxCLK IN) jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle)
AC Timing Diagrams
FIGURE 1. “Worst Case” Test Pattern
5
DS012485-5
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