DS90CF386 Datasheet, PDF (5/16 Pages) National Semiconductor (TI) – +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-85 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-85 MHz

AC Timing Diagrams (Continued)
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FIGURE 3. “16 Grayscale” Test Pattern (DS90CF366)(Notes 5, 6, 7, 8)
Note 5: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 6: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 7: Figures 1, 3 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Note 8: Recommended pin to signal mapping. Customer may choose to define differently.
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FIGURE 4. DS90CF386/DS90CF366 (Receiver) CMOS/TTL Output Load and Transition Times
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FIGURE 5. DS90CF386/DS90CF366 (Receiver) Setup/Hold and High/Low Times
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