DS90CF386 Datasheet, PDF (1/16 Pages) National Semiconductor (TI) – +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-85 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-85 MHz

May 2003
DS90CF386/DS90CF366
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD)
Link—85 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel
Display (FPD) Link—85 MHz
General Description
The DS90CF386 receiver converts the four LVDS data
streams (Up to 2.38 Gbps throughput or 297.5 Megabytes/
sec bandwidth) back into parallel 28 bits of CMOS/TTL data
(24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL).
Also available is the DS90CF366 that converts the three
LVDS data streams (Up to 1.78 Gbps throughput or 223
Megabytes/sec bandwidth) back into parallel 21 bits of
CMOS/TTL data (18 bits of RGB and 3 bits of Hsync, Vsync
and DE). Both Receivers’ outputs are Falling edge strobe. A
Rising edge or Falling edge strobe transmitter (DS90C385/
DS90C365) will interoperate with a Falling edge strobe Re-
ceiver without any translation logic.
The DS90CF386 is also offered in a 64 ball, 0.8mm fine pitch
ball grid array (FBGA) package which provides a 44 %
reduction in PCB footprint compared to the 56L TSSOP
package.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n 20 to 85 MHz shift clock support
n Rx power consumption <142 mW (typ) @85MHz
Grayscale
n Rx Power-down mode <1.44 mW (max)
n ESD rating >7 kV (HBM), >700V (EIAJ)
n Supports VGA, SVGA, XGA and Single Pixel SXGA.
n PLL requires no external components
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 56-lead or 48-lead TSSOP package
n DS90CF386 also available in a 64 ball, 0.8mm fine pitch
ball grid array (FBGA) package
Block Diagrams
DS90CF386
DS90CF366
10108527
Order Number DS90CF386MTD or DS90CF386SLC
See NS Package Number MTD56 or SLC64A
Order Number DS90CF366MTD
See NS Package Number MTD48
10108528
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