DS90C031B_01 Datasheet, PDF (5/11 Pages) National Semiconductor (TI) – LVDS Quad CMOS Differential Line Driver

Parameter Measurement Information (Continued)
Typical Application
FIGURE 5. Driver TRI-STATE Delay Waveform
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FIGURE 6. Point-to-Point Application
Applications Information
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in Figure 6. This configuration provides a clean signaling
environment for the quick edge rates of the drivers. The
receiver is connected to the driver through a balanced media
which may be a standard twisted pair cable, a parallel pair
cable, or simply PCB traces. Typically, the characteristic
impedance of the media is in the range of 100Ω. A termina-
tion resistor of 100Ω should be selected to match the media,
and is located as close to the receiver input pins as possible.
The termination resistor converts the current sourced by the
driver into a voltage that is detected by the receiver. Other
configurations are possible such as a multi-receiver configu-
ration, but the effects of a mid-stream connector(s), cable
stub(s), and other impedance discontinuities as well as
ground shifting, noise margin limits, and total termination
loading must be taken into account.
The DS90C031B differential line driver is a balanced current
source design. A current mode driver, generally speaking
has a high output impedance and supplies a constant cur-
rent for a range of loads (a voltage mode driver on the other
hand supplies a constant voltage for a range of loads).
Current is switched through the load in one direction to
produce a logic state and in the other direction to produce
the other logic state. The typical output current is a mere 3.4
mA with a minimum of 2.5 mA, and a maximum of 4.5 mA.
The current mode requires (as discussed above) that a
resistive termination be employed to terminate the signal
and to complete the loop as shown in Figure 6. AC or
unterminated configurations are not allowed. The 3.4 mA
loop current will develop a differential voltage of 340 mV
across the 100Ω termination resistor which the receiver de-
tects with a 240 mV minimum differential noise margin ne-
glecting resistive line losses (driven signal minus receiver
threshold (340 mV – 100 mV = 240 mV). The signal is
centered around +1.2V (Driver Offset, V_OS) with respect to
ground as shown in Figure 7. Note that the steady-state
voltage (V_SS) peak-to-peak swing is twice the differential
voltage (V_OD) and is typically 680 mV.
The current mode driver provides substantial benefits over
voltage mode drivers, such as an RS-422 driver. Its quies-
cent current remains relatively flat versus switching fre-
quency. Whereas the RS-422 voltage mode driver increases
exponentially in most case between 20 MHz–50 MHz. This
is due to the overlap current that flows between the rails of
the device when the internal gates switch. Whereas the
current mode driver switches a fixed current between its
output without any substantial overlap current. This is similar
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