DS15BR400 Datasheet, PDF (5/11 Pages) National Semiconductor (TI) – 4-Channel LVDS Buffer/Repeater with Pre-Emphasis

Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
LVDS OUTPUT DC SPECIFICATIONS (OUTn±)
V_OD
Differential Output Voltage, R_L = 100Ω external resistor between OUT+ and OUT−
0% Pre-emphasis (Note 6) Figure 1
∆V_OD
Change in V_OD between
Complementary States
V_OS
∆V_OS
Offset Voltage (Note 7)
Change in V_OS between
Complementary States
C_OUT
I_OS
LVDS Output Capacitance
Output Short Circuit Current
OUT+ or OUT− to V_SS
OUT+ or OUT− Short to GND
OUT+ or OUT− Short to VDD
SUPPLY CURRENT (Static)
I_CC
Supply Current
All inputs and outputs enabled and active, terminated
with differential load of 100Ω between OUT+ and OUT-.
PEM = L
I_CCZ
Supply Current - Power
Down Mode
PWDN = L, PEM = L
SWITCHING CHARACTERISTICS — LVDS OUTPUTS
t_LHT
Differential Low to High
Use an alternating 1 and 0 pattern at 200 Mbps, measure
Transition Time (Note 12) between 20% and 80% of V_OD.
t_HLT
Differential High to Low
Figures 2, 4
Transition Time (Note 12)
t_PLHD
t_PHLD
Differential Low to High
Propagation Delay
Differential High to Low
Propagation Delay
Use an alternating 1 and 0 pattern at 200 Mbps, measure
at 50% V_OD between input to output.
Figures 2, 3
t_SKD1
t_SKCC
Pulse Skew (Note 12)
Output Channel to Channel
Skew (Note 12)
|t_PLHD– t_PHLD|
Difference in propagation delay (t_PLHD or t_PHLD) among
all output channels.
t_SKP
Part to Part Skew (Note 12) Common edge, parts at same temp and V_CC
t_JIT
Jitter (0% Pre-emphasis) RJ - Alternating 1 and 0 at 750 MHz (Note 9)
(Note 8)
DJ - K28.5 Pattern, 1.5 Gbps (Note 10)
TJ - PRBS 2²³-1 Pattern, 1.5 Gbps (Note 11)
t_ON
LVDS Output Enable Time Time from PWDN to OUT± change from TRI-STATE to
active.
Figures 5, 6
t_OFF
LVDS Output Disable Time Time from PWDN to OUT± change from active to
TRI-STATE.
Figures 5, 6
250
−35
1.05
−35
Typ
(Note
5)
Max
Units
360 500 mV
35 mV
1.18 1.475 V
35 mV
2.5
pF
−21 −40 mA
6
40 mA
175 215 mA
20 200 µA
170 250 ps
170 250 ps
1.0 2.0 ns
1.0 2.0 ns
10
60
ps
25
75
ps
550 ps
0.5 1.5 ps
14
30
ps
14
31
ps
20
µs
12
ns
Note 5: Typical parameters are measured at V_DD = 3.3V, T_A = 25˚C. They are for reference purposes, and are not production-tested.
Note 6: Differential output voltage V_OD is defined as ABS(OUT+–OUT−). Differential input voltage V_ID is defined as ABS(IN+–IN−).
Note 7: Output offset voltage V_OS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
Note 8: Jitter is not production tested, but guaranteed through characterization on a sample basis.
Note 9: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. Stimulus and fixture Jitter has been subtracted. The input
voltage = V_ID = 500 mV, input common mode voltage = V_ICM = 1.2V, 50% duty cycle at 750 MHz, t_r = t_f = 50 ps (20% to 80%).
Note 10: Deterministic Jitter, or DJ, is a peak to peak value. Stimulus and fixture jitter has been subtracted. The input voltage = V_ID = 500 mV, input common mode
voltage = V_ICM = 1.2V, K28.5 pattern at 1.5 Gbps, t_r = t_f = 50 ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).
Note 11: Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture Jitter has been subtracted. The input voltage
= V_ID = 500 mV, input common mode voltage = V_ICM = 1.2V, 2²³-1 PRBS pattern at 1.5 Gbps, t_r = t_f = 50 ps (20% to 80%).
Note 12: Not production tested. Guaranteed by a statistical analysis on a sample basis at the time of characterization.
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