CD4538BC Datasheet, PDF (5/10 Pages) Fairchild Semiconductor – Dual Precision Monostable

Theory of Operation
FIGURE 2
TL F 6000 – 4
Trigger Operation
The block diagram of the CD4538B is shown in Figure 1
with circuit operation following
As shown in Figures 1 and 2 before an input trigger occurs
the monostable is in the quiescent state with the Q output
low and the timing capacitor C_X completely charged to
V_DD When the trigger input A goes from V_SS to V_DD (while
inputs B and C_D are held to V_DD) a valid trigger is recog-
nized which turns on comparator C1 and N-Channel tran-
sistor N1 j At the same time the output latch is set With
transistor N1 on the capacitor C_X rapidly discharges toward
V_SS until V_REF1 is reached At this point the output of com-
parator C1 changes state and transistor N1 turns off Com-
parator C1 then turns off while at the same time comparator
C2 turns on With transistor N1 off the capacitor C_X begins
to charge through the timing resistor R_X toward V_DD When
the voltage across C_X equals V_REF2 comparator C2 chang-
es state causing the output latch to reset (Q goes low) while
at the same time disabling comparator C2 This ends the
timing cycle with the monostable in the quiescent state
waiting for the next trigger
A valid trigger is also recognized when trigger input B goes
from V_DD to V_SS (while input A is at V_SS and input C_D is at
V_DD) k
It should be noted that in the quiescent state C_X is fully
charged to V_DD causing the current through resistor R_X to
be zero Both comparators are ‘‘off’’ with the total device
current due only to reverse junction leakages An added
feature of the CD4538B is that the output latch is set
via the input trigger without regard to the capacitor voltage
Thus propagation delay from trigger to Q is independent of
the value of C_X R_X or the duty cycle of the input waveform
Retrigger Operation
The CD4538B is retriggered if a valid trigger occurs l fol-
lowed by another valid triggerm before the Q output has
returned to the quiescent (zero) state Any retrigger after
the timing node voltage at pin 2 or 14 has begun to rise from
V_REF1 but has not yet reached V_REF2 will cause an in-
crease in output pulse width T When a valid retrigger is
initiated m the voltage at T2 will again drop to V_REF1 before
progressing along the RC charging curve toward V_DD The
Q output will remain high until time T after the last valid
retrigger
Reset Operation
The CD4538B may be reset during the generation of the
output pulse In the reset mode of operation an input pulse
on C_D sets the reset latch and causes the capacitor to be
fast charged to V_DD by turning on transistor Q1 n When
the voltage on the capacitor reaches V_REF2 the reset latch
will clear and then be ready to accept another pulse If the
C_D input is held low any trigger inputs that occur will be
inhibited and the Q and Q outputs of the output latch will not
change Since the Q output is reset when an input low level
is detected on the C_D input the output pulse T can be made
significantly shorter than the minimum pulse width specifica-
tion
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