DP83907 Datasheet, PDF (43/70 Pages) National Semiconductor (TI) – AT/LANTIC™ II

6 0 Operation of DP83907 (Continued)
Linking Receive Buffer Pages
If the length of the packet exhausts the first 256 byte buffer
the DMA performs a forward link to the next buffer to store
the remainder of the packet For a maximal length packet
the buffer logic will link six buffers to store the entire packet
Buffers cannot be skipped when linking a packet will always
be stored in contiguous buffers Before the next buffer can
be linked the Buffer Management Logic performs two com-
parisons The first comparison tests for equality between
the DMA address of the next buffer and the contents of the
Page Stop Register If the buffer address equals the Page
Stop Register the buffer management logic will restore the
DMA to the first buffer in the Receive Buffer Ring value
programmed in the Page Start Address Register The sec-
ond comparison tests for equality between the DMA ad-
dress of the next buffer address and the contents of the
Boundary Pointer Register If the two values are equal the
reception is aborted The Boundary Pointer Register can be
used to protect against overwrfting any area in the receive
buffer ring that has not yet been read When linking buffers
buffer management will never cross this pointer effectively
avoiding any overwrites If the buffer address does not
match either the Boundary Pointer or Page Stop Address
the link to the next buffer is performed
Linking Buffers
Before the DMA can enter the next contiguous 256 byte
buffer the address is checked for equality to PSTOP and to
the Boundary Pointer If neither are reached the DMA is
allowed to use the next buffer
Buffer Ring Overflow
If the Buffer Ring has been filled and the DMA reaches the
Boundary Pointer Address reception of the incoming pack-
et will be aborted by the DP83907 Thus the packets previ-
ously received and still contained in the Ring will not be
destroyed
In heavily loaded networks which cause overflows of the
Receive Buffer Ring the DP83907 may disable the local
DMA and suspend further receptions even if the Boundary
register is advanced beyond the Current register In the
event that the DP83907 should encounter a receive buffer
overflow it is necessary to implement the following routine
A receive buffer overflow is indicated by the DP83907’s as-
sertion of the overflow bit (OVW) in the Interrupt Status
Register (ISR)
If this routine is not adhered to the DP83907 may act in an
unpredictable manner It should also be noted that it is not
permissible to service an overflow interrupt by continuing to
empty packets from the receive buffer without implementing
the prescribed overflow routine A flow chart of the
DP83907’s overflow routine can be found in Figure 32
Note It is necessary to define a variable in the driver which will be called
‘‘Resend’’
1) Read and store the value of the TXP bit in the
DP83907’s Command Register
2) Issue the STOP command to the DP83907 This is ac-
complished by setting the STP bit in the DP83907’s
Command Register Writing 21H to the Command Reg-
ister will stop the DP83907
3) Wait for at least 1 6 ms Since the DP83907 will com-
plete any transmission or reception that is in progress
it is necessary to time out for the maximum possible
duration of an Ethernet transmission or reception By
waiting 1 6 ms this is achieved with some guard band
added Previously it was recommended that the RST
bit of the nterrupt Status Register be polled to insure
that the pending transmission or reception is complet-
ed This bit is not a reliable indicator and subsequently
should be ignored
TL F 12082 – 26
FIGURE 31 Linking Receive Buffer Pages
43