DP83953 Datasheet, PDF(42/90 Page) National Semiconductor (TI) – Repeater Interface Controller with Security Features, Internal Drivers and Integrated Filters

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DP83953 Datasheet, PDF (42/90 Pages) National Semiconductor (TI) – Repeater Interface Controller with Security Features, Internal Drivers and Integrated Filters

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5.0 HUB MANAGEMENT SUPPORT (Continued)

Packet Status Register 2

OWC NSFD PLER ELBER JAB

CBT9 CBT8

Bit

Symbol

Description

D(1:0)

CT(9:8)

JAB

ELBER

CRER

NSFD

OWC

Collision Timer Bits 9 and 8: These two bits are the upper bits of the collision bit timer.

Jabber Event: This bit indicates that the receive packet was long enough to force the

repeater into the jabber protect state.

Elasticity Buffer Error During the packet an Elasticity Buffer underflow or overflow

condition occurred.

Carrier Error Event: The packet suffered sufficient jitter/noise corruption to cause the

PLL decoder to lose lock.

Non SFD: The repeated packet did not contain a Start of Frame Delimiter. When this bit

is set the Repeat Byte Counter counts the length of the entire packet. When this bit is

not set the byte counter only counts post SFD bytes.

Note: The operation of this bit is not inhibited by the occurrence of a collision during packet repetition (see de-

scription of the Repeat Byte Counter below).

Out of Window Collision: The packet suffered an out of window collision.

Short Event: The received activity was so small it met the criteria to be classed as a

short event.

Modified Packet Status Register 5 (MPS=1 in GSR register)

RIC2A provides an option for a new Packet Status Register 5 (PSR5) field. On the seven bytes of management status

field, PSR5 has been modified to indicate the source address mismatch information (SAM bit) for security purposes.

By using this option, the maximum received byte count changes to 2048 (211). As soon as the counter reaches this num-

ber, it will freeze, instead of rolling over and starting again on the reception of the next packet.

A RUNT bit has also been added to this register indicating whether the last packet received by a port was RUNT. (A

packet is RUNT when its length is greater than or equal to Short Event and less than or equal to 64 bytes from SFD.)

The other registers comprise the remainder of the collision timer register [PSR(3)], the Repeat Byte Count registers

[PSR(4) and PSR(5)], and the Inter Frame Gap Counter "IFG" register [PSR(6)].

Modified Packet Status Register 5 (MPS=1 in GSR register)

resv

SAM

RUNT RBY10 RBY9

RBY8

Bit

R/W

D[7:5] NA

Symbol

RBY8

RBY9

RBY10

RUNT

SAM

resv

Description

Eighth bit of receive byte count

Ninth bit of receive byte count

Tenth bit of receive byte count

RUNT: A packet whose length is less or equal to 64 bytes from SFD and

greater than or equal to SE length.

0: Last packet received was not a runt

1: Last packet received was a runt

Source Address Mismatch:

0: Source address match occurred for the last packet

1: Source address mismatch occurred for the last packet

Reserved for Future Use: reads as a logic 0

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