COP888XG Datasheet, PDF (41/53 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 4k to 24k Memory, Comparators and USART

MICROWIRE/PLUS (Continued)
FIGURE 20. MICROWIRE/PLUS Application
Memory Map
All RAM, ports and registers (except A and PC) are mapped into data memory address space.
DS012829-20
Address
S/ADD REG
0000 to 006F
0070 to 007F
xx80 to xx93
xx94
xx95
xx96
xx97 to xxAF
xxB0
xxB1
xxB2
xxB3
xxB4
xxB5
xxB6
xxB7
xxB8
xxB9
xxBA
xxBB
Contents
On-Chip RAM bytes (112 bytes)
Unused RAM Address Space (Reads As
All Ones)
Unused RAM Address Space (Reads
Undefined Data)
Port F data register, PORTFD
Port F configuration register, PORTFC
Port F input pins (read only), PORTFP
Unused address space (Reads
Undefined Data)
Timer T3 Lower Byte
Timer T3 Upper Byte
Timer T3 Autoload Register T3RA Lower
Byte
Timer T3 Autoload Register T3RA Upper
Byte
Timer T3 Autoload Register T3RB Lower
Byte
Timer T3 Autoload Register T3RB Upper
Byte
Timer T3 Control Register
Comparator Select Register
(Reg:CMPSL)
UART Transmit Buffer (Reg:TBUF)
UART Receive Buffer (Reg:RBUF)
UART Control and Status Register
(Reg:ENU)
UART Receive Control and Status
Register (Reg:ENUR)
Address
S/ADD REG
xxBC
xxBD
xxBE
xxBF
xxC0
xxC1
xxC2
xxC3
xxC4
xxC5
xxC6
xxC7
xxC8
xxC9
xxCA
xxCB to xxCF
xxD0
xxD1
xxD2
xxD3
xxD4
xxD5
Contents
UART Interrupt and Clock Source
Register (Reg:ENUI)
UART Baud Register (Reg:BAUD)
UART Prescale Select Register
(Reg:PSR)
Reserved for UART
Timer T2 Lower Byte
Timer T2 Upper Byte
Timer T2 Autoload Register T2RA Lower
Byte
Timer T2 Autoload Register T2RA Upper
Byte
Timer T2 Autoload Register T2RB Lower
Byte
Timer T2 Autoload Register T2RB Upper
Byte
Timer T2 Control Register
WATCHDOG Service Register
(Reg:WDSVR)
MIWU Edge Select Register
(Reg:WKEDG)
MIWU Enable Register (Reg:WKEN)
MIWU Pending Register (Reg:WKPND)
Reserved
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
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